Patents by Inventor Elliot H. Mednick
Elliot H. Mednick has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11880260Abstract: A heterogeneous processor system includes a first processor implementing an instruction set architecture (ISA) including a set of ISA features and configured to support a first subset of the set of ISA features. The heterogeneous processor system also includes a second processor implementing the ISA including the set of ISA features and configured to support a second subset of the set of ISA features, wherein the first subset and the second subset of the set of ISA features are different from each other. When the first subset includes an entirety of the set of ISA features, the lower-feature second processor is configured to execute an instruction thread by consuming less power and with lower performance than the first processor.Type: GrantFiled: June 25, 2020Date of Patent: January 23, 2024Assignee: Advanced Micro Devices, Inc.Inventors: Elliot H. Mednick, Edward McLellan
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Publication number: 20240004721Abstract: An apparatus and method for efficiently performing power management for a multi-client computing system. In various implementations, a computing system includes multiple clients that process tasks corresponding to applications. The clients store generated requests of a particular type while processing tasks. A client receives an indication specifying that another client is having requests of the particular type being serviced. In response to receiving this indication, the client inserts a first urgency level in one or more stored requests of the particular type prior to sending the requests for servicing. When the client determines a particular time interval has elapsed, the client sends an indication to other clients specifying that requests of the particular type are being serviced. The client also inserts a second urgency level different from the first urgency level in one or more stored requests of the particular type prior to sending the requests for servicing.Type: ApplicationFiled: June 29, 2022Publication date: January 4, 2024Inventors: Indrani Paul, Alexander J. Branover, Benjamin Tsien, Elliot H. Mednick
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Publication number: 20230185623Abstract: A method, system, and apparatus determines whether a task should be relocated from a first processor to a second processor by comparing performance metrics to associated thresholds or by using other indications. The task is relocated from the first processor to the second processor and executed on the second processor based on the com paring.Type: ApplicationFiled: February 3, 2023Publication date: June 15, 2023Applicant: Advanced Micro Devices, Inc.Inventors: Alexander J. Branover, Benjamin Tsien, Elliot H. Mednick
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Patent number: 11586472Abstract: A method, system, and apparatus determines that one or more tasks should be relocated from a first processor to a second processor by comparing performance metrics to associated thresholds or by using other indications. To relocate the one or more tasks from the first processor to the second processor, the first processor is stalled and state information from the first processor is copied to the second processor. The second processor uses the state information and then services incoming tasks instead of the first processor.Type: GrantFiled: December 10, 2019Date of Patent: February 21, 2023Assignee: Advanced Micro Devices, Inc.Inventors: Alexander J. Branover, Benjamin Tsien, Elliot H. Mednick
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Patent number: 11347650Abstract: A method includes, for each data value in a set of one or more data values, determining a boundary between a high order portion of the data value and a low order portion of the data value, storing the low order portion at a first memory location utilizing a low data fidelity storage scheme, and storing the high order portion at a second memory location utilizing a high data fidelity storage scheme for recording data at a higher data fidelity than the low data fidelity storage scheme.Type: GrantFiled: February 7, 2018Date of Patent: May 31, 2022Assignee: Advanced Micro Devices, Inc.Inventors: David A. Roberts, Elliot H. Mednick
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Patent number: 11216250Abstract: A method includes providing a set of one or more computational units implemented in a set of one or more field programmable gate array (FPGA) devices, where the set of one or more computational units is configured to generate a plurality of output values based on one or more input values. The method further includes, for each computational unit of the set of computational units, performing a first calculation in the computational unit using a first number representation, where a first output of the plurality of output values is based on the first calculation, determining a second number representation based on the first output value, and performing a second calculation in the computational unit using the second number representation, where a second output of the plurality of output values is based on the second calculation.Type: GrantFiled: December 6, 2017Date of Patent: January 4, 2022Assignee: Advanced Micro Devices, Inc.Inventors: Nicholas P. Malaya, Elliot H. Mednick
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Publication number: 20210173715Abstract: A method, system, and apparatus determines that one or more tasks should be relocated from a first processor to a second processor by comparing performance metrics to associated thresholds or by using other indications. To relocate the one or more tasks from the first processor to the second processor, the first processor is stalled and state information from the first processor is copied to the second processor. The second processor uses the state information and then services incoming tasks instead of the first processor.Type: ApplicationFiled: December 10, 2019Publication date: June 10, 2021Applicant: Advanced Micro Devices, Inc.Inventors: Alexander J. Branover, Benjamin Tsien, Elliot H. Mednick
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Publication number: 20200409762Abstract: A method and apparatus for servicing a task in a computer system includes receiving the task and if the task is serviceable without waking the fabric, servicing the task by a first service stage entity. If the task is not serviceable by the first service stage entity, the task is serviced by a first processing unit without waking a second processing unit. If the task is not serviceable by the first processing unit, the task is serviced by the second processing unit.Type: ApplicationFiled: June 26, 2019Publication date: December 31, 2020Applicant: Advanced Micro Devices, Inc.Inventors: Alexander J. Branover, Elliot H. Mednick, Benjamin Tsien
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Publication number: 20200393887Abstract: A heterogeneous processor system includes a first processor implementing an instruction set architecture (ISA) including a set of ISA features and configured to support a first subset of the set of ISA features. The heterogeneous processor system also includes a second processor implementing the ISA including the set of ISA features and configured to support a second subset of the set of ISA features, wherein the first subset and the second subset of the set of ISA features are different from each other. When the first subset includes an entirety of the set of ISA features, the lower-feature second processor is configured to execute an instruction thread by consuming less power and with lower performance than the first processor.Type: ApplicationFiled: June 25, 2020Publication date: December 17, 2020Inventors: Elliot H. MEDNICK, Edward MCLELLAN
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Patent number: 10698472Abstract: A heterogeneous processor system includes a first processor implementing an instruction set architecture (ISA) including a set of ISA features and configured to support a first subset of the set of ISA features. The heterogeneous processor system also includes a second processor implementing the ISA including the set of ISA features and configured to support a second subset of the set of ISA features, wherein the first subset and the second subset of the set of ISA features are different from each other. When the first subset includes an entirety of the set of ISA features, the lower-feature second processor is configured to execute an instruction thread by consuming less power and with lower performance than the first processor.Type: GrantFiled: October 27, 2017Date of Patent: June 30, 2020Assignee: ADVANCED MICRO DEVICES, INC.Inventors: Elliot H. Mednick, Edward McLellan
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Patent number: 10452548Abstract: A method of preemptive cache writeback includes transmitting, from a first cache controller of a first cache to a second cache controller of a second cache, an unused bandwidth message representing an unused bandwidth between the first cache and the second cache during a first cycle. During a second cycle, a cache line containing dirty data is preemptively written back from the second cache to the first cache based on the unused bandwidth message. Further, the cache line in the second cache is written over in response to a cache miss to the second cache.Type: GrantFiled: September 28, 2017Date of Patent: October 22, 2019Assignee: Advanced Micro Devices, Inc.Inventors: David A. Roberts, Elliot H. Mednick
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Publication number: 20190243772Abstract: A method includes, for each data value in a set of one or more data values, determining a boundary between a high order portion of the data value and a low order portion of the data value, storing the low order portion at a first memory location utilizing a low data fidelity storage scheme, and storing the high order portion at a second memory location utilizing a high data fidelity storage scheme for recording data at a higher data fidelity than the low data fidelity storage scheme.Type: ApplicationFiled: February 7, 2018Publication date: August 8, 2019Inventors: David A. Roberts, Elliot H. Mednick
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Publication number: 20190171420Abstract: A method includes providing a set of one or more computational units implemented in a set of one or more field programmable gate array (FPGA) devices, where the set of one or more computational units is configured to generate a plurality of output values based on one or more input values. The method further includes, for each computational unit of the set of computational units, performing a first calculation in the computational unit using a first number representation, where a first output of the plurality of output values is based on the first calculation, determining a second number representation based on the first output value, and performing a second calculation in the computational unit using the second number representation, where a second output of the plurality of output values is based on the second calculation.Type: ApplicationFiled: December 6, 2017Publication date: June 6, 2019Inventors: Nicholas P. Malaya, Elliot H. Mednick
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Patent number: 10289413Abstract: A hybrid floating-point arithmetic processor includes a scheduler, a hybrid register file, and a hybrid arithmetic operation circuit. The scheduler has an input for receiving floating-point instructions, and an output for providing decoded register numbers in response to the floating-point instructions. The hybrid register file is coupled to the scheduler and contains circuitry for storing a plurality of floating-point numbers each represented by a digital sign bit, a digital exponent, and an analog mantissa. The hybrid register file has an output for providing selected ones of the plurality of floating-point numbers in response to the decoded register numbers. The hybrid arithmetic operation circuit is coupled to the scheduler and to the hybrid register file, for performing a hybrid arithmetic operation between two floating-point numbers selected by the scheduler and providing a hybrid result represented by a result digital sign bit, a result digital exponent, and a result analog mantissa.Type: GrantFiled: December 15, 2017Date of Patent: May 14, 2019Assignee: Advanced Micro Devices, Inc.Inventors: David A. Roberts, Elliot H. Mednick, David John Cownie
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Publication number: 20190129489Abstract: A heterogeneous processor system includes a first processor implementing an instruction set architecture (ISA) including a set of ISA features and configured to support a first subset of the set of ISA features. The heterogeneous processor system also includes a second processor implementing the ISA including the set of ISA features and configured to support a second subset of the set of ISA features, wherein the first subset and the second subset of the set of ISA features are different from each other. When the first subset includes an entirety of the set of ISA features, the lower-feature second processor is configured to execute an instruction thread by consuming less power and with lower performance than the first processor.Type: ApplicationFiled: October 27, 2017Publication date: May 2, 2019Inventors: Elliot H. MEDNICK, Edward MCLELLAN
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Publication number: 20190102175Abstract: A hybrid floating-point arithmetic processor includes a scheduler, a hybrid register file, and a hybrid arithmetic operation circuit. The scheduler has an input for receiving floating-point instructions, and an output for providing decoded register numbers in response to the floating-point instructions. The hybrid register file is coupled to the scheduler and contains circuitry for storing a plurality of floating-point numbers each represented by a digital sign bit, a digital exponent, and an analog mantissa. The hybrid register file has an output for providing selected ones of the plurality of floating-point numbers in response to the decoded register numbers. The hybrid arithmetic operation circuit is coupled to the scheduler and to the hybrid register file, for performing a hybrid arithmetic operation between two floating-point numbers selected by the scheduler and providing a hybrid result represented by a result digital sign bit, a result digital exponent, and a result analog mantissa.Type: ApplicationFiled: December 15, 2017Publication date: April 4, 2019Applicant: Advanced Micro Devices, Inc.Inventors: David A. Roberts, Elliot H. Mednick, David John Cownie
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Publication number: 20190095330Abstract: A method of preemptive cache writeback includes transmitting, from a first cache controller of a first cache to a second cache controller of a second cache, an unused bandwidth message representing an unused bandwidth between the first cache and the second cache during a first cycle. During a second cycle, a cache line containing dirty data is preemptively written back from the second cache to the first cache based on the unused bandwidth message. Further, the cache line in the second cache is written over in response to a cache miss to the second cache.Type: ApplicationFiled: September 28, 2017Publication date: March 28, 2019Inventors: David A. ROBERTS, Elliot H. MEDNICK
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Patent number: 10209991Abstract: A system and method for reducing latencies of main memory data accesses are described. A non-blocking load (NBLD) instruction identifies an address of requested data and a subroutine. The subroutine includes instructions dependent on the requested data. A processing unit verifies that address translations are available for both the address and the subroutine. The processing unit continues processing instructions with no stalls caused by younger-in-program-order instructions waiting for the requested data. The non-blocking load unit performs a cache coherent data read request on behalf of the NBLD instruction and requests that the processing unit perform an asynchronous jump to the subroutine upon return of the requested data from lower-level memory.Type: GrantFiled: November 16, 2016Date of Patent: February 19, 2019Assignees: Advanced Micro Devices, Inc., ATI Technologies ULCInventors: Meenakshi Sundaram Bhaskaran, Elliot H. Mednick, David A. Roberts, Anthony Asaro, Amin Farmahini-Farahani
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Patent number: 10164639Abstract: A macro scheduler includes a resource tracking module configured to update a database enumerating a plurality of macro components of a set of field programmable gate array (FPGA) devices, a communication interface configured to receive from a first client device a first design definition indicating one or more specified macro components for a design, resource allocation logic configured to allocate a first set of macro components for the design by allocating one of the plurality of macro components for each of the one or more specified macro components indicated in the first design definition, and configuration logic configured to implement the design in the set of FPGA devices by configuring the first set of allocated macro components according to the first design definition.Type: GrantFiled: November 14, 2017Date of Patent: December 25, 2018Assignee: Advanced Micro Devices, Inc.Inventors: David A. Roberts, Andrew G. Kegel, Elliot H. Mednick
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Publication number: 20170212760Abstract: A system and method for reducing latencies of main memory data accesses are described. A non-blocking load (NBLD) instruction identifies an address of requested data and a subroutine. The subroutine includes instructions dependent on the requested data. A processing unit verifies that address translations are available for both the address and the subroutine. The processing unit continues processing instructions with no stalls caused by younger-in-program-order instructions waiting for the requested data. The non-blocking load unit performs a cache coherent data read request on behalf of the NBLD instruction and requests that the processing unit perform an asynchronous jump to the subroutine upon return of the requested data from lower-level memory.Type: ApplicationFiled: November 16, 2016Publication date: July 27, 2017Inventors: Meenakshi Sundaram Bhaskaran, Elliot H. Mednick, David A. Roberts, Anthony Asaro, Amin Farmahini-Farahani