Patents by Inventor Emi Kawashima

Emi Kawashima has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200266304
    Abstract: A laminated body comprising a substrate, one or more layers selected from a contact resistance reducing layer and a reduction suppressing layer, a Schottky electrode layer and a metal oxide semiconductor layer in this order.
    Type: Application
    Filed: December 26, 2016
    Publication date: August 20, 2020
    Applicant: IDEMITSU KOSAN CO., LTD.
    Inventors: Yoshihiro UEOKA, Takashi SEKIYA, Shigekazu TOMAI, Emi KAWASHIMA, Yuki TSURUMA, Motohiro TAKESHIMA
  • Publication number: 20200140337
    Abstract: A sintered oxide contains In element, Y element, and Ga element at respective atomic ratios as defined in formulae (1) to (3) below, 0.80?In/(In+Y+Ga)?0.96??(1), 0.02?Y/(In+Y+Ga)?0.10??(2), and 0.02?Ga/(In+Y+Ga)?0.10??(3), and Al element at an atomic ratio as defined in a formula (4) below, 0.005?Al/(In+Y+Ga+Al)?0.07??(4), where In, Y, Ga, and Al in the formulae represent the number of atoms of the In element, Y element, Ga element, and Al element in the sintered oxide, respectively.
    Type: Application
    Filed: March 29, 2018
    Publication date: May 7, 2020
    Applicant: IDEMITSU KOSAN CO., LTD.
    Inventors: Kazuyoshi INOUE, Masatoshi SHIBATA, Emi KAWASHIMA, Yuki TSURUMA, Shigekazu TOMAI
  • Patent number: 10374045
    Abstract: A semiconductor device 1 which comprises a pair of an ohmic electrode 20 and a Schottky electrode 10 separated from each other, and a semiconductor layer 30 in contact with the ohmic electrode 20 and the Schottky electrode 10, and which satisfies the following formula (I): n < ? ? ? V e qL 2 ( I ) in which n is a carrier concentration (cm?3) of the semiconductor layer, ? is a dielectric constant (F/cm) of the semiconductor layer, Ve is a forward effective voltage (V) between the ohmic electrode and the Schottky electrode, q is an elementary charge (C), and L is a distance (cm) between the ohmic electrode and the Schottky electrode.
    Type: Grant
    Filed: December 21, 2016
    Date of Patent: August 6, 2019
    Assignee: IDEMITSU KOSAN CO., LTD.
    Inventors: Yuki Tsuruma, Takashi Sekiya, Shigekazu Tomai, Emi Kawashima, Yoshihiro Ueoka
  • Publication number: 20190237556
    Abstract: A structure including a metal oxide semiconductor layer and a noble metal oxide layer, wherein the metal oxide semiconductor layer and the noble metal oxide layer are adjacent to each other, and a film thickness of the noble metal oxide layer is more than 10 nm.
    Type: Application
    Filed: October 11, 2017
    Publication date: August 1, 2019
    Applicant: Idemitsu Kosan Co., Ltd.
    Inventors: Yuki TSURUMA, Emi KAWASHIMA, Yoshikazu NAGASAKI, Takashi SEKIYA, Yoshihiro UEOKA
  • Patent number: 10340356
    Abstract: A laminated body comprising a substrate, an ohmic electrode layer, a metal oxide semiconductor layer, a Schottky electrode layer and a buffer electrode layer in this order, wherein a reduction suppressing layer is provided between the Schottky electrode layer and the buffer electrode layer.
    Type: Grant
    Filed: December 26, 2016
    Date of Patent: July 2, 2019
    Assignee: IDEMITSU KOSAN CO., LTD.
    Inventors: Emi Kawashima, Takashi Sekiya, Yuki Tsuruma, Yoshihiro Ueoka, Shigekazu Tomai, Motohiro Takeshima
  • Publication number: 20190013389
    Abstract: A laminated body comprising a substrate, an ohmic electrode layer, a metal oxide semiconductor layer, a Schottky electrode layer and a buffer electrode layer in this order, wherein a reduction suppressing layer is provided between the Schottky electrode layer and the buffer electrode layer.
    Type: Application
    Filed: December 26, 2016
    Publication date: January 10, 2019
    Applicant: IDEMITSU KOSAN CO., LTD.
    Inventors: Emi KAWASHIMA, Takashi SEKIYA, Yuki TSURUMA, Yoshihiro UEOKA, Shigekazu TOMAI, Motohiro TAKESHIMA
  • Publication number: 20190006473
    Abstract: A semiconductor device 1 which comprises a pair of an ohmic electrode 20 and a Schottky electrode 10 separated from each other, and a semiconductor layer 30 in contact with the ohmic electrode 20 and the Schottky electrode 10, and which satisfies the following formula (I): n < ? ? ? V e qL 2 ( I ) in which n is a carrier concentration (cm?3) of the semiconductor layer, ? is a dielectric constant (F/cm) of the semiconductor layer, Ve is a forward effective voltage (V) between the ohmic electrode and the Schottky electrode, q is an elementary charge (C), and L is a distance (cm) between the ohmic electrode and the Schottky electrode.
    Type: Application
    Filed: December 21, 2016
    Publication date: January 3, 2019
    Applicant: IDEMITSU KOSAN CO., LTD.
    Inventors: Yuki TSURUMA, Takashi SEKIYA, Shigekazu TOMAI, Emi KAWASHIMA, Yoshihiro UEOKA
  • Publication number: 20170263786
    Abstract: A schottky barrier diode element having a silicon (Si) substrate, an oxide semiconductor layer and a schottky electrode layer, wherein the oxide semiconductor layer includes a polycrystalline and/or amorphous oxide semiconductor having a band gap of 3.0 eV or more and 5.6 eV or less.
    Type: Application
    Filed: May 25, 2017
    Publication date: September 14, 2017
    Applicant: IDEMITSU KOSAN CO., LTD.
    Inventors: Shigekazu TOMAI, Masatoshi SHIBATA, Emi KAWASHIMA, Koki YANO, Hiromi HAYASAKA
  • Patent number: 9691910
    Abstract: A schottky barrier diode element having a silicon (Si) substrate, an oxide semiconductor layer and a schottky electrode layer, wherein the oxide semiconductor layer includes a polycrystalline and/or amorphous oxide semiconductor having a band gap of 3.0 eV or more and 5.6 eV or less.
    Type: Grant
    Filed: August 8, 2014
    Date of Patent: June 27, 2017
    Assignee: IDEMITSU KOSAN CO., LTD.
    Inventors: Shigekazu Tomai, Masatoshi Shibata, Emi Kawashima, Koki Yano, Hiromi Hayasaka
  • Publication number: 20170141240
    Abstract: A Schottky barrier diode element includes an n-type or p-type silicon (Si) substrate, an oxide semiconductor layer, and a Schottky electrode layer, the oxide semiconductor layer including either or both of a polycrystalline oxide that includes gallium (Ga) as the main component and an amorphous oxide that includes gallium (Ga) as the main component.
    Type: Application
    Filed: December 28, 2016
    Publication date: May 18, 2017
    Applicant: IDEMITSU KOSAN CO., LTD.
    Inventors: Shigekazu TOMAI, Masatoshi SHIBATA, Emi KAWASHIMA, Koki YANO, Hiromi HAYASAKA
  • Patent number: 9570631
    Abstract: A Schottky barrier diode element includes an n-type or p-type silicon (Si) substrate, an oxide semiconductor layer, and a Schottky electrode layer, the oxide semiconductor layer including either or both of a polycrystalline oxide that includes gallium (Ga) as the main component and an amorphous oxide that includes gallium (Ga) as the main component.
    Type: Grant
    Filed: August 8, 2014
    Date of Patent: February 14, 2017
    Assignee: IDEMITSU KOSAN CO., LTD.
    Inventors: Shigekazu Tomai, Masatoshi Shibata, Emi Kawashima, Koki Yano, Hiromi Hayasaka
  • Publication number: 20160211386
    Abstract: A Schottky barrier diode element includes an n-type or p-type silicon (Si) substrate, an oxide semiconductor layer, and a Schottky electrode layer, the oxide semiconductor layer including either or both of a polycrystalline oxide that includes gallium (Ga) as the main component and an amorphous oxide that includes gallium (Ga) as the main component.
    Type: Application
    Filed: August 8, 2014
    Publication date: July 21, 2016
    Applicant: IDEMITSU KOSAN CO., LTD.
    Inventors: Shigekazu TOMAI, Masatoshi SHIBATA, Emi KAWASHIMA, Koki YANO, Hiromi HAYASAKA
  • Publication number: 20160197202
    Abstract: A schottky barrier diode element having a silicon (Si) substrate, an oxide semiconductor layer and a schottky electrode layer, wherein the oxide semiconductor layer includes a polycrystalline and/or amorphous oxide semiconductor having a band gap of 3.0 eV or more and 5.6 eV or less.
    Type: Application
    Filed: August 8, 2014
    Publication date: July 7, 2016
    Applicant: IDEMITSU KOSAN CO., LTD.
    Inventors: Shigekazu TOMAI, Masatoshi SHIBATA, Emi KAWASHIMA, Koki YANO, Hiromi HAYASAKA
  • Publication number: 20130264565
    Abstract: A semiconductor thin film includes one or more amorphous metal oxides, an OH group being bonded to at least some of the metal atoms of the amorphous metal oxides.
    Type: Application
    Filed: October 11, 2011
    Publication date: October 10, 2013
    Inventors: Mami Nishimura, Emi Kawashima, Masashi Kasami, Masahide Matsuura, Masayuki Itose