Abstract: A die comprising a body of semiconductor material, said body configured to receive a solder layer of gold containing alloy for use in die bonding said die to a substrate, wherein the die includes an interface layer on a surface of the body for receiving the solder layer, the interface layer having a plurality of sub-layers of different metals.

Abstract: Disclosed is a discrete semiconductor device package (100) comprising a semiconductor die (110) having a first surface and a second surface opposite said first surface carrying a contact (112); a conductive body (120) on said contact; an encapsulation material (130) laterally encapsulating said conductive body; and a capping member (140, 610) such as a solder cap, a further semiconductor die or a combination thereof in conductive contact with the solder portion, said solder cap extending over the encapsulation material. A further solder cap (150) may be provided over the first surface. A method of manufacturing such a discrete semiconductor device package is also disclosed.

Abstract: Consistent with an example embodiment, a semiconductor device comprises a patterned conductive layer defining contact pads for being connected to terminals of a semiconductor chip. The semiconductor chip comprises the terminals at a first side and an adhesive layer at a second side opposite to the first side; wherein, the semiconductor chip is mounted with an adhesive layer on a patterned conductive layer such that the semiconductor chip part of each respective contact pad leaves part thereof uncovered by the chip for wire bonding. Wire bonds connect respective terminals of the semiconductor chip and respective contact pads at the first side thereof. A molding compound covers the semiconductor chip, the wire bonds and the contact pads; wherein, the molding compound is also located on the second side of the semiconductor device, separating the contact regions that are located directly on a backside of the contact pads.

Abstract: A die comprising a body of semiconductor material, said body configured to receive a solder layer of gold containing alloy for use in die bonding said die to a substrate, wherein the die includes an interface layer on a surface of the body for receiving the solder layer, the interface layer having a plurality of sub-layers of different metals.

Abstract: Disclosed is a discrete semiconductor device package (100) comprising a semiconductor die (110) having a first surface and a second surface opposite said first surface carrying a contact (112); a conductive body (120) on said contact; an encapsulation material (130) laterally encapsulating said conductive body; and a capping member (140, 610) such as a solder cap, a further semiconductor die or a combination thereof in conductive contact with the solder portion, said solder cap extending over the encapsulation material. A further solder cap (150) may be provided over the first surface. A method of manufacturing such a discrete semiconductor device package is also disclosed.

Abstract: Disclosed is a discrete semiconductor device package (100) comprising a semiconductor die (110) having a first surface and a second surface opposite said first surface carrying a contact (112); a conductive body (120) on said contact; an encapsulation material (130) laterally encapsulating said conductive body; and a capping member (140, 610) such as a solder cap, a further semiconductor die or a combination thereof in conductive contact with the solder portion, said solder cap extending over the encapsulation material. A further solder cap (150) may be provided over the first surface. A method of manufacturing such a discrete semiconductor device package is also disclosed.

Abstract: Consistent with an example embodiment, a semiconductor device comprises a patterned conductive layer defining contact pads for being connected to terminals of a semiconductor chip. The semiconductor chip comprises the terminals at a first side and an adhesive layer at a second side opposite to the first side; wherein, the semiconductor chip is mounted with an adhesive layer on a patterned conductive layer such that the semiconductor chip part of each respective contact pad leaves part thereof uncovered by the chip for wire bonding. Wire bonds connect respective terminals of the semiconductor chip and respective contact pads at the first side thereof. A molding compound covers the semiconductor chip, the wire bonds and the contact pads; wherein, the molding compound is also located on the second side of the semiconductor device, separating the contact regions that are located directly on a backside of the contact pads.

Abstract: The invention relates to a method of manufacturing a semiconductor device, the method comprising: i) providing a substrate carrier comprising a substrate layer and a patterned conductive layer, wherein the patterned conductive layer defines contact pads; ii) partially etching the substrate carrier using the patterned conductive layer as a mask defining contact regions in the substrate layer; iii) providing the semiconductor chip; iv) mounting said semiconductor chip with the adhesive layer on the patterned conductive layer such that the semiconductor chip covers at least one of the trenches and part of the contact pads neighboring the respective trench are left uncovered for future wire bonding; v) providing wire bonds between respective terminals of the semiconductor chip and respective contact pads of the substrate carrier; vi) providing a molding compound covering the substrate carrier and the semiconductor chip, and vii) etching the backside (S2) of the substrate carrier to expose the molding compound in

Abstract: Disclosed is a discrete semiconductor device package (100) comprising a semiconductor die (110) having a first surface and a second surface opposite said first surface carrying a contact (112); a conductive body (120) on said contact; an encapsulation material (130) laterally encapsulating said conductive body; and a capping member (140, 610) such as a solder cap, a further semiconductor die or a combination thereof in conductive contact with the solder portion, said solder cap extending over the encapsulation material. A further solder cap (150) may be provided over the first surface. A method of manufacturing such a discrete semiconductor device package is also disclosed.

Abstract: Disclosed is a discrete semiconductor device package (100) comprising a leadframe portion (10) comprising a recess (14) having a depth substantially equal to the thickness of the discrete semiconductor device (20), wherein a raised portion of the leadframe portion adjacent to said recess defines a first contact area (12); a discrete semiconductor device (20) in said recess, wherein the exposed surface (22) of the discrete semiconductor device defines a second contact area; a protective layer (30) covering the leadframe portion and the a discrete semiconductor device but not the first contact area and the second contact area; and respective plating layers (40) covering the first contact area and the second contact area. A method of manufacturing such a package and a carrier comprising such a package are also disclosed.

Abstract: Disclosed is a method of manufacturing a discrete semiconductor device package (100), comprising providing a wafer comprising a plurality of semiconductor devices (50), each of said semiconductor devices comprising a substrate (110) having a top contact (130) and a bottom contact (150); partially sawing said wafer with a first sawing blade such that the semiconductor devices are partially separated from each other by respective incisions (20); lining said incisions with an electrically insulating film (160); and sawing through said incisions with a second sawing blade such that the semiconductor devices are fully separated from each other. A resulting discrete semiconductor device package (100) and a carrier (200) comprising such a discrete semiconductor device package (100) are also disclosed.

Abstract: The invention relates to a method of manufacturing a semiconductor device, the method comprising: i) providing a substrate carrier comprising a substrate layer and a patterned conductive layer, wherein the patterned conductive layer defines contact pads; ii) partially etching the substrate carrier using the patterned conductive layer as a mask defining contact regions in the substrate layer; iii) providing the semiconductor chip; iv) mounting said semiconductor chip with the adhesive layer on the patterned conductive layer such that the semiconductor chip covers at least one of the trenches and part of the contact pads neighboring the respective trench are left uncovered for future wire bonding; v) providing wire bonds between respective terminals of the semiconductor chip and respective contact pads of the substrate carrier; vi) providing a molding compound covering the substrate carrier and the semiconductor chip, and vii) etching the backside (S2) of the substrate carrier to expose the molding compound in