Patents by Inventor Emil Gizdarski

Emil Gizdarski has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10908213
    Abstract: A proposed linear time compactor (LTC) with a means of significantly reducing the X-masking effect for designs with X's and supports high levels of test data compression where: 1) The LTC consists of two parts that are unloaded into a tester through an output serializer. 2) The first part is unloaded per t shift cycles while the second part is unloaded once per test pattern. 3) One part of the LTC divides scan chains into groups such that X-masking effect between groups of scan chains is impossible. 4) One part of LTC divides shift cycles into groups such that X-masking effect between groups of shift cycles is impossible. Consequently, the X-masking effect in the proposed LTC is significantly reduced.
    Type: Grant
    Filed: September 27, 2019
    Date of Patent: February 2, 2021
    Assignee: Synopsys, Inc.
    Inventors: Emil Gizdarski, Peter Wohl, John A. Waicukauski
  • Patent number: 10380303
    Abstract: Dynamic power-aware encoding method and apparatus is presented based on a various embodiments described herein. The experimental results confirmed that a desirable reduction in the toggling rate in the decompressed test stimulus is achievable by reasonable overhead (ATPG time, hardware overhead and pattern inflation) typically without degradation of a compression ratio. The performed experimental evaluation confirms that the described embodiments can support aggressive scan compression, efficient dynamic pattern compaction and a reduction of toggling rate in the decompressed test stimulus.
    Type: Grant
    Filed: November 30, 2015
    Date of Patent: August 13, 2019
    Assignee: Synopsys, Inc.
    Inventor: Emil Gizdarski
  • Patent number: 10345369
    Abstract: Decompressor circuitry includes a first segment and a second segment each comprising memory elements (MEs) and (i) said first segment receives the plurality of static variables originating from the tester, and (ii) and said second segment, receives the plurality of dynamic variables originating from the tester.
    Type: Grant
    Filed: October 2, 2013
    Date of Patent: July 9, 2019
    Assignee: Synopsys, Inc.
    Inventor: Emil Gizdarski
  • Publication number: 20170154132
    Abstract: Dynamic power-aware encoding method and apparatus is presented based on a various embodiments described herein. The experimental results confirmed that a desirable reduction in the toggling rate in the decompressed test stimulus is achievable by reasonable overhead (ATPG time, hardware overhead and pattern inflation) typically without degradation of a compression ratio. The performed experimental evaluation confirms that the described embodiments can support aggressive scan compression, efficient dynamic pattern compaction and a reduction of toggling rate in the decompressed test stimulus.
    Type: Application
    Filed: November 30, 2015
    Publication date: June 1, 2017
    Applicant: SYNOPSYS, INC.
    Inventor: EMIL GIZDARSKI
  • Patent number: 9404972
    Abstract: Patterns used to detect a failure in a semiconductor chip are analyzed to determine a subset of logic in a design where a semiconductor chip, fabricated based on the design, contains a fault in the subset. Parts of the semiconductor chip can be pre-calculated to identify a key subsection of logic, based on the patterns, with that subsection being stored in a computer readable file. Good-machine simulation is performed on the subsection of logic using truncated rank-ordered simulation. The results are compared to the results of the testing of the physical semiconductor chip.
    Type: Grant
    Filed: October 5, 2015
    Date of Patent: August 2, 2016
    Assignee: Synopsys, Inc.
    Inventors: Peter Wohl, John A Waicukauski, Emil Gizdarski, Wolfgang Meyer, Andrea Costa
  • Publication number: 20160025810
    Abstract: Patterns used to detect a failure in a semiconductor chip are analyzed to determine a subset of logic in a design where a semiconductor chip, fabricated based on the design, contains a fault in the subset. Parts of the semiconductor chip can be pre-calculated to identify a key subsection of logic, based on the patterns, with that subsection being stored in a computer readable file. Good-machine simulation is performed on the subsection of logic using truncated rank-ordered simulation. The results are compared to the results of the testing of the physical semiconductor chip.
    Type: Application
    Filed: October 5, 2015
    Publication date: January 28, 2016
    Inventors: Peter Wohl, John A. Waicukauski, Emil Gizdarski, Wolfgang Meyer, Andrea Costa
  • Patent number: 9171123
    Abstract: Patterns used to detect a failure in a semiconductor chip are analyzed to determine a subset of logic in a design where a semiconductor chip, fabricated based on the design, contains a fault in the subset. Parts of the semiconductor chip can be pre-calculated to identify a key subsection of logic, based on the patterns, with that subsection being stored in a computer readable file. Good-machine simulation is performed on the subsection of logic using truncated rank-ordered simulation. The results are compared to the results of the testing of the physical semiconductor chip.
    Type: Grant
    Filed: August 30, 2013
    Date of Patent: October 27, 2015
    Assignee: Synopsys, Inc.
    Inventors: Peter Wohl, John A Waicukauski, Emil Gizdarski, Wolfgang Meyer, Andrea Costa
  • Publication number: 20150067629
    Abstract: Patterns used to detect a failure in a semiconductor chip are analyzed to determine a subset of logic in a design where a semiconductor chip, fabricated based on the design, contains a fault in the subset. Parts of the semiconductor chip can be pre-calculated to identify a key subsection of logic, based on the patterns, with that subsection being stored in a computer readable file. Good-machine simulation is performed on the subsection of logic using truncated rank-ordered simulation. The results are compared to the results of the testing of the physical semiconductor chip.
    Type: Application
    Filed: August 30, 2013
    Publication date: March 5, 2015
    Applicant: Synopsys, Inc.
    Inventors: Peter Wohl, John A. Waicukauski, Emil Gizdarski, Wolfgang Meyer, Andrea Costa
  • Patent number: 8707227
    Abstract: Methods and apparatuses for synthesizing a multimode x-tolerant compressor are described.
    Type: Grant
    Filed: November 23, 2011
    Date of Patent: April 22, 2014
    Assignee: Synopsys, Inc.
    Inventor: Emil Gizdarski
  • Publication number: 20140095101
    Abstract: Decompressor circuitry includes a first segment and a second segment each comprising memory elements (MEs) and (i) said first segment receives the plurality of static variables originating from the tester, and (ii) and said second segment, receives the plurality of dynamic variables originating from the tester.
    Type: Application
    Filed: October 2, 2013
    Publication date: April 3, 2014
    Applicant: Synopsys, Inc.
    Inventor: Emil Gizdarski
  • Publication number: 20120072879
    Abstract: Methods and apparatuses for synthesizing a multimode x-tolerant compressor are described.
    Type: Application
    Filed: November 23, 2011
    Publication date: March 22, 2012
    Applicant: Synopsys, Inc.
    Inventor: Emil Gizdarski
  • Patent number: 8103926
    Abstract: Methods and apparatuses for synthesizing and/or implementing an augmented multimode compactor are described.
    Type: Grant
    Filed: December 22, 2010
    Date of Patent: January 24, 2012
    Assignee: Synopsys, Inc.
    Inventor: Emil Gizdarski
  • Patent number: 7949921
    Abstract: Methods and apparatuses for synthesizing and/or implementing an augmented multimode compactor are described. An integrated circuit has circuitry that compacts test response data from scan chains in the integrated circuit under test. In many cases groups of the scan chains are coupled to output registers, such that a same group of scan chains is coupled to sequential elements of different output registers; and the same group is a subset of the scan chains including two or more scan chains. Various computer-implemented methods divide scan chains among at least groups and partitions. The groups disallow sharing a common scan chain from the scan chains, within a particular partition. At least one common scan chain is shared between the groups of different partitions.
    Type: Grant
    Filed: September 22, 2008
    Date of Patent: May 24, 2011
    Assignee: Synopsys, Inc.
    Inventor: Emil Gizdarski
  • Publication number: 20110093752
    Abstract: Methods and apparatuses for synthesizing and/or implementing an augmented multimode compactor are described.
    Type: Application
    Filed: December 22, 2010
    Publication date: April 21, 2011
    Applicant: Synopsys, Inc.
    Inventor: Emil Gizdarski
  • Patent number: 7900105
    Abstract: A low overhead dynamically reconfigurable shared scan-in test architecture is provided. This test architecture advantageously allows for changing scan inputs during the scan operation on a per shift basis. The flexibility of reconfiguring the scan input to scan chain mapping every shift cycle can advantageously reduce both test data volume and test application time.
    Type: Grant
    Filed: May 12, 2010
    Date of Patent: March 1, 2011
    Assignee: Synopsys, Inc.
    Inventors: Rohit Kapur, Nodari Sitchinava, Samitha Samaranayake, Emil Gizdarski, Frederic J. Neuveux, Suryanarayana Duggirala, Thomas W. Williams
  • Patent number: 7882409
    Abstract: Proposed are methods and apparatuses for synthesis of a new class of compressors called augmented multimode compactors, capable of achieving a flexible trade-off between compaction ratio, observability, control data volume and diagnostic properties in the presence of a large number of unknown values. The augmented multimode compactors reduce and/or completely avoid the X-masking effect in the compacted test responses. In addition, a requirement for constructing compactors is that any single error in the test response produces a unique erroneous signature within S consecutive shift cycles where the erroneous signature is calculated as a difference between the faulty signature and the fault-free signature.
    Type: Grant
    Filed: October 31, 2008
    Date of Patent: February 1, 2011
    Assignee: Synopsys, Inc.
    Inventor: Emil Gizdarski
  • Patent number: 7836367
    Abstract: A low overhead dynamically reconfigurable shared scan-in test architecture is provided. This test architecture advantageously allows for changing scan inputs during the scan operation on a per shift basis. The flexibility of reconfiguring the scan input to scan chain mapping every shift cycle can advantageously reduce both test data volume and test application time.
    Type: Grant
    Filed: August 11, 2009
    Date of Patent: November 16, 2010
    Assignee: Synopsys, Inc.
    Inventors: Rohit Kapur, Nodari Sitchinava, Samitha Samaranayake, Emil Gizdarski, Frederic J. Neuveux, Suryanarayana Duggirala, Thomas W. Williams
  • Patent number: 7836368
    Abstract: A low overhead dynamically reconfigurable shared scan-in test architecture is provided. This test architecture advantageously allows for changing scan inputs during the scan operation on a per shift basis. The flexibility of reconfiguring the scan input to scan chain mapping every shift cycle can advantageously reduce both test data volume and test application time.
    Type: Grant
    Filed: August 24, 2009
    Date of Patent: November 16, 2010
    Assignee: Synopsys, Inc.
    Inventors: Rohit Kapur, Nodari Sitchinava, Samitha Samaranayake, Emil Gizdarski, Frederic J. Neuveux, Suryanarayana Duggirala, Thomas W. Williams
  • Publication number: 20100223516
    Abstract: A low overhead dynamically reconfigurable shared scan-in test architecture is provided. This test architecture advantageously allows for changing scan inputs during the scan operation on a per shift basis. The flexibility of reconfiguring the scan input to scan chain mapping every shift cycle can advantageously reduce both test data volume and test application time.
    Type: Application
    Filed: May 12, 2010
    Publication date: September 2, 2010
    Applicant: Synopsys, Inc.
    Inventors: Rohit Kapur, Nodari Sitchinava, Samitha Samaranayake, Emil Gizdarski, Frederic Neuveux, Suryanarayana Duggirala, Thomas W. Williams
  • Patent number: 7774663
    Abstract: A low overhead dynamically reconfigurable shared scan-in test architecture is provided. This test architecture advantageously allows for changing scan inputs during the scan operation on a per shift basis. The flexibility of reconfiguring the scan input to scan chain mapping every shift cycle can advantageously reduce both test data volume and test application time.
    Type: Grant
    Filed: July 9, 2009
    Date of Patent: August 10, 2010
    Assignee: Synopsys, Inc.
    Inventors: Rohit Kapur, Nodari Sitchinava, Samitha Samaranayake, Emil Gizdarski, Frederic J. Neuveux, Suryanarayana Duggirala, Thomas W. Williams