Abstract: A serial data clock receiver circuit (11) is provided that synchronizes a clock signal to data. The serial data clock receiver circuit (11) comprises a control circuit (21), a dual oscillator circuit (19), and a phase locked loop circuit (22). The control circuit (21) arms the dual oscillator circuit (19) for being enabled during an idle period. The phase locked loop circuit (22) provides a reference voltage for the dual oscillator circuit (19). The dual oscillator circuit (19) is responsive to both the data and control circuit (19) for providing a clock signal.

Abstract: The driver circuit comprises drive means (Q2) for drawing an output current from a bus line (13) in a first state of the circuit. An output diode (S1) in the path of the output current is reverse biased in a second state of the circuit to isolate the drive means from the bus line. A control current (I.sub.Q2B) for the drive transistor is drawn from the bus line (13), beyond the output diode (S1). By this means, power dissipation (heat) within the driver circuit due to the control current is eliminated. The driver circuit also comprises means (26, S3, P1) for biasing the output during connection of the circuit to a live bus line, so as to reduce noise for other circuits connected to the bus line.