Abstract: Branching of the data-flow in a mask data preparation processes is described herein. In various implementations, the output stream from a first mask data processing operation is branched. Subsequently, the branched output stream may be connected to the input stream of a first independent mask data preparation operation and a second independent mask data preparation operation. This provides that the first and the second independent mask data preparation operations may operate in parallel. Furthermore, this provides that the first and the second independent mask data preparation operations may operate upon discrete “portions” of the data processed by the first mask data preparation operation.

Abstract: Methods for jointly calibrating etch and exposure mask process models from etch only data are described. Initially, an etch model and an exposure model may be identified. Subsequently, a combined etch/exposure model may be generated based upon the etch model and the exposure model. Following which, a global optimization process may be performed to calibrate the combined etch/exposure model based upon measured data representing the etch and the exposure effects. With some implementations, the global optimization process is based in part upon a cost function representing the norm of the difference between the simulated mask contours and the measured mask contours. Furthermore, in some implementations, the optimization variable set is the union of the parameter sets corresponding to the etch model and the exposure model individually. Further still, with various implementations, the optimization of based upon the etch parameter set is “nested” inside an optimization of the exposure parameter set, or, vice versa.

Abstract: Methods for jointly calibrating etch and exposure mask process models from etch only data are described. Initially, an etch model and an exposure model may be identified. Subsequently, a combined etch/exposure model may be generated based upon the etch model and the exposure model. Following which, a global optimization process may be performed to calibrate the combined etch/exposure model based upon measured data representing the etch and the exposure effects. With some implementations, the global optimization process is based in part upon a cost function representing the norm of the difference between the simulated mask contours and the measured mask contours. Furthermore, in some implementations, the optimization variable set is the union of the parameter sets corresponding to the etch model and the exposure model individually. Further still, with various implementations, the optimization of based upon the etch parameter set is “nested” inside an optimization of the exposure parameter set, or, vice versa.

Abstract: Branching of the data-flow in a mask data preparation processes is described herein. In various implementations, the output stream from a first mask data processing operation is branched. Subsequently, the branched output stream may be connected to the input stream of a first independent mask data preparation operation and a second independent mask data preparation operation. This provides that the first and the second independent mask data preparation operations may operate in parallel. Furthermore, this provides that the first and the second independent mask data preparation operations may operate upon discrete “portions” of the data processed by the first mask data preparation operation.

Abstract: Techniques are described for reducing the number of shots in a fractured layout design. Each polygon in a layout design is examined for “jogs.” For each identified jog, the surrounding region is examined to determine if there is an opposing jog or parallel edge that can be aligned with the identified jog. The surrounding region then is examined for any polygon features, such as edges or vertices, which might restrict or prevent the alignment of the identified jog with the opposing jog or edge. If the identified jog can be aligned with an opposing jog or edge without violating a specified alignment constraint, then those jogs are deemed an alignable jog pair. Next, one or more of the alignable jog pairs is selected for alignment. The alignable jog pairs may be selected for alignment based upon their impact on the size of the polygon when aligned. Once one or more of the alignable jog pairs have been selected, then the layout design data will be modified to align the selected jog pairs.

Abstract: Layout correction is accomplished using a forward mapping technique. Forward mapping refers to mapping of fragments from a reticle layout to a target layout, while backward mapping refers to mapping of fragments from the target layout to the reticle layout. Forward mapping provides a technique for making an unambiguous mapping for each reticle fragment to a corresponding target layout fragment. The mapping does not necessarily provide a one-to-one correspondence between reticle fragments and target layout fragments. That is, multiple reticle layout fragments can map to a single target layout fragment. An edge placement error for the target layout fragments is used to make positioning corrections for the corresponding reticle fragment(s). Edge placement error can be determined, for example, with a simulation process that simulates a manufacturing process using the reticles.

Abstract: A tool for optimizing the layout of a microdevice adds fragmentation points to polygons in a first hierarchical database layer in a manner suitable for application of a tool to apply a resolution enhancement technique (RET) such as optical and process correction (OPC). Portions of polygons in a database level that interact with polygons of a second level in the database are promoted to the second database level, and refragmented. The RET operates on the polygons of the first and second levels of the database to determine how polygons of each of the first and second levels should be adjusted, if necessary, such that the layout is optimized.

Abstract: Layout correction is accomplished using a forward mapping technique. Forward mapping refers to mapping of fragments from a reticle layout to a target layout, while backward mapping refers to mapping of fragments from the target layout to the reticle layout. Forward mapping provides a technique for making an unambiguous mapping for each reticle fragment to a corresponding target layout fragment. The mapping does not necessarily provide a one-to-one correspondence between reticle fragments and target layout fragments. That is, multiple reticle layout fragments can map to a single target layout fragment. An edge placement error for the target layout fragments is used to make positioning corrections for the corresponding reticle fragment(s). Edge placement error can be determined, for example, with a simulation process that simulates a manufacturing process using the reticles.

Abstract: A method and apparatus for translating a hierarchical IC layout file into a format that can be used by a mask writer that accepts files having a limited hierarchy. Cover cells of the original IC layout file or a modified file are designated, and the hierarchical file is redefined to include only those designated cover cells. Non-designated cover cells and other geometric data are flattened into the designated cover cells. The hierarchy of the modified file is then redefined to be less than or equal to the hierarchy limit of the mask writing tool.

Abstract: Layout correction is accomplished using a forward mapping technique. Forward mapping refers to mapping of fragments from a reticle layout to a target layout, while backward mapping refers to mapping of fragments from the target layout to the reticle layout. Forward mapping provides a technique for making an unambiguous mapping for each reticle fragment to a corresponding target layout fragment. The mapping does not necessarily provide a one-to-one correspondence between reticle fragments and target layout fragments. That is, multiple reticle layout fragments can map to a single target layout fragment. An edge placement error for the target layout fragments is used to make positioning corrections for the corresponding reticle fragment(s). Edge placement error can be determined, for example, with a simulation process that simulates a manufacturing process using the reticles.

Abstract: An integrated verification and manufacturability tool provides more efficient verification of integrated device designs than verification using several different verification tools. The integrated verification and manufacturability includes a hierarchical database to store shared design data accessed by multiple verification tool components (e.g., layout versus schematic, design rule check, optical process correction, phase shift mask assignment and machine language conversion). The hierarchical database includes representations of one or more additional, or intermediate layer structures that are created and used by the verification tool components for operations performed on the design being verified. Use of a single hierarchical database having shared data for access and use by multiple verification components streamlines the verification process, which provides an improved verification tool.

Abstract: A method and apparatus for translating a hierarchical IC layout file into a format that can be used by a mask writer that accepts files having a limited hierarchy. Cover cells of the original IC layout file or a modified file are designated, and the hierarchical file is redefined to include only those designated cover cells. Non-designated cover cells and other geometric data are flattened into the designated cover cells. The hierarchy of the modified file is then redefined to be less than or equal to the hierarchy limit of the mask writing tool.

Abstract: A method of translating device layout data to a format for a mask writing tool includes the acts of reading a file defining a number of cells that represent structures on the device. One or more cells are selected and one or more modified cells based on the interaction of the selected cells with other cells in the device layout are created. One or more additional cells is created that will create structures on the mask that are not formed by writing files corresponding to the modified cells and areas that prevent extraneous structures from being formed on the mask at a selected location by the writing of the files corresponding to the modified cells. A jobdeck for the mask writing tool is created that indicates where the files corresponding to modified cells and the one or more additional cells should be written to create one or more masks or reticles.

Abstract: A tool for optimizing the layout of a microdevice adds fragmentation points to polygons in a first hierarchical database layer in a manner suitable for application of a tool to apply a resolution enhancement technique (RET) such as optical and process correction (OPC). Portions of polygons in a database level that interact with polygons of a second level in the database are promoted to the second database level, and refragmented. The RET operates on the polygons of the first and second levels of the database to determine how polygons of each of the first and second levels should be adjusted, if necessary, such that the layout is optimized.

Abstract: Layout correction is accomplished using a forward mapping technique. Forward mapping refers to mapping of fragments from a reticle layout to a target layout, while backward mapping refers to mapping of fragments from the target layout to the reticle layout. Forward mapping provides a technique for making an unambiguous mapping for each reticle fragment to a corresponding target layout fragment. The mapping does not necessarily provide a one-to-one correspondence between reticle fragments and target layout fragments. That is, multiple reticle layout fragments can map to a single target layout fragment. An edge placement error for the target layout fragments is used to make positioning corrections for the corresponding reticle fragment(s). Edge placement error can be determined, for example, with a simulation process that simulates a manufacturing process using the reticles.

Abstract: A tool for optimizing the layout of a microdevice adds fragmentation points to polygons in a first hierarchical database layer in a manner suitable for application of a tool to apply a resolution enhancement technique (RET) such as optical and process correction (OPC). Portions of polygons in a database level that interact with polygons of a second level in the database are promoted to the second database level, and refragmented. The RET operates on the polygons of the first and second levels of the database to determine how polygons of each of the first and second levels should be adjusted, if necessary, such that the layout is optimized.

Abstract: A tool for optimizing the layout of a microdevice adds fragmentation points to polygons in a first hierarchical database layer in a manner suitable for application of a tool to apply a resolution enhancement technique (RET) such as optical and process correction (OPC). Portions of polygons in a database level that interact with polygons of a second level in the database are promoted to the second database level, and refragmented. The RET operates on the polygons of the first and second levels of the database to determine how polygons of each of the first and second levels should be adjusted, if necessary, such that the layout is optimized.

Abstract: Layout correction is accomplished using a forward mapping technique. Forward mapping refers to mapping of fragments from a reticle to a target layout, while backward mapping refers to mapping of fragments from the target layout to the reticle. Forward mapping provides a technique for making an unambiguous mapping for each reticle fragment to a corresponding target layout fragment. The mapping does not necessarily provide a one-to-one correspondence between reticle fragments and target layout fragments. That is, multiple reticle fragments can map to a single target layout fragment. An edge placement error for the target layout fragments is used to make positioning corrections for the corresponding reticle fragment(s). Edge placement error can be determined, for example, with a simulation process that simulates a manufacturing process using the reticles.

Abstract: A method of translating device layout data to a format for a mask writing tool includes the acts of reading a file defining a number of cells that represent structures on the device. One or more cells are selected and one or more modified cells based on the interaction of the selected cells with other cells in the device layout are created. One or more additional cells is created that will create structures on the mask that are not formed by writing files corresponding to the modified cells and areas that prevent extraneous structures from being formed on the mask at a selected location by the writing of the files corresponding to the modified cells. A jobdeck for the mask writing tool is created that indicates where the files corresponding to modified cells and the one or more additional cells should be written to create one or more masks or reticles.

Abstract: Layout correction is accomplished using a forward mapping technique. Forward mapping refers to mapping of fragments from a reticle layout to a target layout, while backward mapping refers to mapping of fragments from the target layout to the reticle layout. Forward mapping provides a technique for making an unambiguous mapping for each reticle fragment to a corresponding target layout fragment. The mapping does not necessarily provide a one-to-one correspondence between reticle fragments and target layout fragments. That is, multiple reticle layout fragments can map to a single target layout fragment. An edge placement error for the target layout fragments is used to make positioning corrections for the corresponding reticle fragment(s). Edge placement error can be determined, for example, with a simulation process that simulates a manufacturing process using the reticles.