Patents by Inventor Emmanuel Augendre

Emmanuel Augendre has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10147788
    Abstract: A process for fabricating a gate-wrap-around field-effect transistor is provided, including: providing a superposition of first to third nanowires, each made of a semiconductor, the second nanowire being subjected to a strain along its longitudinal axis, a median portion of the first to third nanowires being covered by a sacrificial gate; forming voids by removing a portion of the first and third nanowires that is intermediate between their ends and their median portion, while preserving the superposition of the first to third nanowires level with the ends and under the sacrificial gate; forming an electrical insulator in the voids around the second nanowire; removing the sacrificial gate and the median portion of the first and third nanowires; and forming a gate electrode wrapped around the median portion of the second nanowire.
    Type: Grant
    Filed: October 12, 2017
    Date of Patent: December 4, 2018
    Assignee: Commissariat A L'Energie Atomique et aux Energies Alternatives
    Inventors: Emmanuel Augendre, Remi Coquand, Shay Reboh
  • Patent number: 10141424
    Abstract: Method of manufacturing a structure with semiconducting bars suitable for forming one at least one transistor channel, including the following steps: a) make a semiconducting structure, composed of an alternation of first bars based on a first material and second bars based on a second material, the second material being a semiconducting material, then b) remove exposed portions of the structure based on the first material through an opening in a mask formed on the structure, the removal being made by selective etching in the opening of the first material relative to the second material, so as to expose a space around the second bars, then c) grow a given semiconducting material (25) around the second bars (6c) in the opening, the given semiconducting material having a mesh parameter different from the mesh parameter of the second material (7) so as to induce a strain on the sheaths based on the given semiconducting material.
    Type: Grant
    Filed: May 24, 2017
    Date of Patent: November 27, 2018
    Assignees: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, IBM CORPORATION
    Inventors: Remi Coquand, Emmanuel Augendre, Nicolas Loubet, Shay Reboh
  • Patent number: 10134875
    Abstract: The invention relates to a process for fabricating a vertical transistor, comprising the step of providing a substrate surmounted by a stack of first, second and third layers made of first, second and third semiconductors, respectively, said second semiconductor being different from the first and third semiconductors. The process further includes horizontally growing first, second and third dielectric layers, by oxidation, from the first, second and third semiconductor layers, respectively, with a second dielectric layer, the thickness of which differs from the thickness of said first and third dielectric layers and removing the second dielectric layer so as to form a recess that is vertically self-aligned with the second semiconductor layer, which recess is positioned vertically between first and second blocks that are made facing the first and third semiconductor layers. Finally, the process includes forming a gate stack in said self-aligned recess.
    Type: Grant
    Filed: December 14, 2017
    Date of Patent: November 20, 2018
    Assignee: Commissariat a l'Energie Atomique et aux Energies Alternatives
    Inventors: Shay Reboh, Emmanuel Augendre, Remi Coquand
  • Patent number: 10109735
    Abstract: A process for fabricating a gate-wrap-around field-effect transistor is provided, including: providing a superposition of first to third nanowires, each made of a semiconductor, the second nanowire being subjected to a strain along its longitudinal axis, a median portion of the first to third nanowires being covered by a sacrificial gate; forming voids by removing a portion of the first and third nanowires that is intermediate between their ends and their median portion, while preserving the superposition of the first to third nanowires level with the ends and under the sacrificial gate; forming an electrical insulator in the voids around the second nanowire; removing the sacrificial gate and the median portion of the first and third nanowires; and forming a gate electrode wrapped around the median portion of the second nanowire.
    Type: Grant
    Filed: October 12, 2017
    Date of Patent: October 23, 2018
    Assignee: Commissariat A L'Energie Atomique et aux Energies Alternatives
    Inventors: Remi Coquand, Emmanuel Augendre, Shay Reboh
  • Publication number: 20180301341
    Abstract: A process for fabricating a gate-wrap-around field-effect transistor is provided, including providing a substrate surmounted with first and second nanowires extending in a same longitudinal direction and having a median portion covered by a first material, and first and second ends that are arranged on either side of the median portion, a periphery of which is covered by respective first and second dielectric spacers made of a second material that is different from the first material, the ends having exposed lateral faces; doping a portion of the first and second ends via the lateral faces; depositing an amorphous silicon alloy on the first and second lateral faces followed by crystallizing the alloy; and depositing a metal on either side of the nanowires to form first and second metal contacts that respectively make electrical contact with the doped portions of the first and second ends of the nanowires.
    Type: Application
    Filed: March 28, 2018
    Publication date: October 18, 2018
    Applicant: Commissariat a l'energie atomique et aux energies alternatives
    Inventors: Remi COQUAND, Emmanuel AUGENDRE, Shay REBOH
  • Patent number: 10096694
    Abstract: A process for fabricating a vertical transistor is provided, including steps of providing a substrate surmounted by a stack of first to third layers made of first to third semiconductors materials of two different types; partially etching the first and third layers with an etching that is selective, so as to form a first void in the first layer and a third void in the third layer, extending to the lower surface and to the upper surface of the second layer, respectively; filling the voids in order to form spacers making contact with the lower surface and the upper surface, respectively; partially etching the second layer with an etching that is selective, so as to form a second void between the first and second spacers; and depositing a conductor material in the second void.
    Type: Grant
    Filed: May 1, 2017
    Date of Patent: October 9, 2018
    Assignee: Commissariat A L'Energie Atomique et aux Energies Alternatives
    Inventors: Remi Coquand, Emmanuel Augendre, Shay Reboh
  • Publication number: 20180204931
    Abstract: The invention relates to a process for fabricating a vertical transistor, comprising the step of providing a substrate surmounted by a stack of first, second and third layers made of first, second and third semiconductors, respectively, said second semiconductor being different from the first and third semiconductors. The process further includes horizontally growing first, second and third dielectric layers, by oxidation, from the first, second and third semiconductor layers, respectively, with a second dielectric layer, the thickness of which differs from the thickness of said first and third dielectric layers and removing the second dielectric layer so as to form a recess that is vertically self-aligned with the second semiconductor layer, which recess is positioned vertically between first and second blocks that are made facing the first and third semiconductor layers. Finally, the process includes forming a gate stack in said self-aligned recess.
    Type: Application
    Filed: December 14, 2017
    Publication date: July 19, 2018
    Applicant: Commissariat a l'energie atomique et aux energies alternatives
    Inventors: Shay REBOH, Emmanuel AUGENDRE, Remi COQUAND
  • Publication number: 20180182893
    Abstract: A process for fabricating a gate-wrap-around field-effect transistor is provided, including: providing a superposition of first to third nanowires, each made of a semiconductor, the second nanowire being subjected to a strain along its longitudinal axis, a median portion of the first to third nanowires being covered by a sacrificial gate; forming voids by removing a portion of the first and third nanowires that is intermediate between their ends and their median portion, while preserving the superposition of the first to third nanowires level with the ends and under the sacrificial gate; forming an electrical insulator in the voids around the second nanowire; removing the sacrificial gate and the median portion of the first and third nanowires; and forming a gate electrode wrapped around the median portion of the second nanowire.
    Type: Application
    Filed: October 12, 2017
    Publication date: June 28, 2018
    Applicant: Commissariat a l'energie atomique et aux energies alternatives
    Inventors: Remi COQUAND, Emmanuel AUGENDRE, Shay REBOH
  • Publication number: 20180175166
    Abstract: Method for producing a semiconductor device, comprising: producing a stack including a first crystalline semiconductor portion intended to form a channel and arranged on at least one second portion which can be selectively etched vis-à-vis the first portion, producing a dummy gate and external spacers, etching the stack, a remaining part of the stack under the dummy gate and the external spacers being conserved, producing source/drain by epitaxy from the remaining part of the stack; removing the dummy gate and the second portion, oxidising portions of the source/drain from the parts of the source/drain revealed by the removal of the second portion, forming internal spacers, producing a gate electrically insulated from the source/drain by the external and internal spacers.
    Type: Application
    Filed: December 11, 2017
    Publication date: June 21, 2018
    Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Shay Reboh, Emmanuel Augendre, Remi Coquand
  • Publication number: 20180175194
    Abstract: A method for making a semiconductor device, including: a) etching a stack of a layer of a second semiconductor, which is crystalline, arranged between a substrate and a layer of a first semiconductor, which is crystalline, the second semiconductor being different from the first semiconductor and subjected to a compressive stress, forming a nanowire stack, b) making a dummy gate and outer spacers, covering a part of the nanowire stack which is formed by portions of the nanowires, c) etching the nanowire stack such that only said part of the stack is preserved, d) removing the portion of the second semiconductor nanowire, e) depositing, in a space formed by this removal, a sacrificial material portion, f) making source and drain regions and inner spacers, g) removing the dummy gate and the sacrificial material portion, h) making a gate.
    Type: Application
    Filed: December 11, 2017
    Publication date: June 21, 2018
    Applicants: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Shay Reboh, Emmanuel Augendre, Remi Coquand, Nicolas Loubet
  • Publication number: 20180175163
    Abstract: Method for making a semiconductor device, comprising: a) making of a stack of crystalline semiconductor layers comprising a first layer and a second layer capable of being selectively etched in relation to the first layer, b) etching of part of the stack, a portion of the first layer forms a nanowire (132) arranged on the second layer, c) selective etching of second layer, d) making, beneath the nanowire, of a sacrificial portion which has an etching selectivity which is greater than that of the second layer, e) making of a sacrificial gate and of an external spacer surrounding the sacrificial gate, f) etching of the stack, revealing ends of the nanowire and of the sacrificial portion aligned with the external spacer, g) selective etching of parts of the sacrificial portion, from its ends, forming aligned cavities beneath the external spacer, h) making of an internal spacer within the cavities.
    Type: Application
    Filed: December 11, 2017
    Publication date: June 21, 2018
    Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Sylvain BARRAUD, Emmanuel Augendre, Remi Coquand, Shay Reboh
  • Publication number: 20180175167
    Abstract: A method for making a semiconductor device, including: a) making, on a substrate, a stack comprising a first semiconductor portion able to form an active zone and arranged between two second portions of a material able to be selectively etched relative to the semiconductor of the first portion, b) making, on a part of the stack, outer spacers and a dummy gate, c) etching the second portions such that remaining parts are arranged under the dummy gate, d) partially oxidising the remaining parts from the outer faces, forming inner spacers, e) removing the dummy gate and non-oxidised parts of the remaining parts arranged under the dummy gate, f) making a gate between the outer spacers and between the inner spacers and covering the channel.
    Type: Application
    Filed: December 11, 2017
    Publication date: June 21, 2018
    Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Shay REBOH, Emmanuel AUGENDRE, Remi COQUAND
  • Patent number: 9997394
    Abstract: A method of transferring a thin layer from a first substrate to a second substrate with different coefficients of thermal expansion, including: providing at least one intermediate layer which temperature is increased by induction when an electromagnetic field is applied to it, more than a temperature increase in the first and second substrates; making contact between the first substrate and the second substrate, with the at least one intermediate layer interposed between them; fracturing the first substrate at a weakened zone making use of supply of thermal energy at the weakened zone made by applying an electromagnetic field to a heterostructure formed by making contact between the first substrate and the second substrate, the application generating local induction heating in the intermediate layer that induces a temperature gradient with a local value at the weakened zone activating the fracture mechanism.
    Type: Grant
    Filed: June 27, 2014
    Date of Patent: June 12, 2018
    Assignee: Commissariat à l'énergie atomique et aux énergies alternatives
    Inventors: Thomas Signamarcheix, Emmanuel Augendre, Lamine Benaissa
  • Publication number: 20180108733
    Abstract: A process for fabricating a gate-wrap-around field-effect transistor is provided, including: providing a superposition of first to third nanowires, each made of a semiconductor, the second nanowire being subjected to a strain along its longitudinal axis, a median portion of the first to third nanowires being covered by a sacrificial gate; forming voids by removing a portion of the first and third nanowires that is intermediate between their ends and their median portion, while preserving the superposition of the first to third nanowires level with the ends and under the sacrificial gate; forming an electrical insulator in the voids around the second nanowire; removing the sacrificial gate and the median portion of the first and third nanowires; and forming a gate electrode wrapped around the median portion of the second nanowire.
    Type: Application
    Filed: October 12, 2017
    Publication date: April 19, 2018
    Applicant: Commissariat a l'energie atomique et aux energies alternatives
    Inventors: Emmanuel Augendre, Remi Coquand, Shay Reboh
  • Patent number: 9917153
    Abstract: A crystalline layer is produced from a crystalline substrate made from a first material on which a masking layer has previously been deposited; the masking layer containing at least one trench forming an access to the substrate, by: forming a crystalline buffer layer situated at least partly in the trench in the masking layer, extending from the substrate and forming a projection beyond the masking layer so that an upper part of the lateral flanks of said buffer layer is left uncovered, the formation step comprising a growth of the buffer layer from the substrate, and forming a crystalline epitaxial layer in a second material, different from the material of the buffer layer, by growth from said upper part of the lateral flanks of the buffer layer left uncovered.
    Type: Grant
    Filed: June 29, 2015
    Date of Patent: March 13, 2018
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Emmanuel Augendre, Thierry Baron
  • Patent number: 9853124
    Abstract: Method of making a transistor with semiconducting nanowires, including: making a semiconducting nanowire on a support, one portion of the nanowire being covered by a dummy gate, in which the dummy gate and the nanowire are surrounded by a dielectric layer, removing the dummy gate, forming a first space surrounded by first parts of the dielectric layer, making an ion implantation in a second part of the dielectric layer under said first portion, said first parts protecting third parts of the dielectric layer, etching said second part, forming a second space, making a gate in the spaces, and a dielectric portion on the gate and said first parts, making an ion implantation in fourth parts of the dielectric layer surrounding second portions of the nanowire, the dielectric portion protecting said first and third parts, etch said fourth parts.
    Type: Grant
    Filed: November 15, 2016
    Date of Patent: December 26, 2017
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Sylvain Barraud, Emmanuel Augendre, Sylvain Maitrejean, Nicolas Posseme
  • Patent number: 9853130
    Abstract: A method of modifying a strain state of a first channel structure in a transistor is provided, said structure being formed from superposed semiconducting elements, the method including providing on a substrate at least one first semiconducting structure formed from a semiconducting stack including alternating elements based on at least one first semiconducting material and elements based on at least one second semiconducting material different from the first material; then removing portions of the second material from the first semiconducting structure by selective etching, the removed portions forming at least one empty space; filling the empty space with a dielectric material; forming a straining zone on the first semiconducting structure based on a first strained material having an intrinsic strain; and performing thermal annealing to cause the dielectric material to creep, and to cause a change in a strain state of the elements based on the first material.
    Type: Grant
    Filed: February 22, 2016
    Date of Patent: December 26, 2017
    Assignee: Commissariat á l'énergie atomique et aux énergies alternatives
    Inventors: Sylvain Maitrejean, Emmanuel Augendre, Jean-Charles Barbe, Benoit Mathieu, Yves Morand
  • Publication number: 20170345915
    Abstract: Method of manufacturing a structure with semiconducting bars suitable for forming one at least one transistor channel, including the following steps: a) make a semiconducting structure, composed of an alternation of first bars based on a first material and second bars based on a second material, the second material being a semiconducting material, then b) remove exposed portions of the structure based on the first material through an opening in a mask formed on the structure, the removal being made by selective etching in the opening of the first material relative to the second material, so as to expose a space around the second bars, then c) grow a given semiconducting material (25) around the second bars (6c) in the opening, the given semiconducting material having a mesh parameter different from the mesh parameter of the second material (7) so as to induce a strain on the sheaths based on the given semiconducting material.
    Type: Application
    Filed: May 24, 2017
    Publication date: November 30, 2017
    Applicants: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, IBM CORPORATION
    Inventors: Remi COQUAND, Emmanuel AUGENDRE, Nicolas LOUBET, Shay REBOH
  • Publication number: 20170330958
    Abstract: A process for fabricating a vertical transistor is provided, including steps of providing a substrate surmounted by a stack of first to third layers made of first to third semiconductors materials of two different types; partially etching the first and third layers with an etching that is selective, so as to form a first void in the first layer and a third void in the third layer, extending to the lower surface and to the upper surface of the second layer, respectively; filling the voids in order to form spacers making contact with the lower surface and the upper surface, respectively; partially etching the second layer with an etching that is selective, so as to form a second void between the first and second spacers; and depositing a conductor material in the second void.
    Type: Application
    Filed: May 1, 2017
    Publication date: November 16, 2017
    Applicant: Commissariat a l'energie atomique et aux energies alternatives
    Inventors: Remi COQUAND, Emmanuel AUGENDRE, Shay REBOH
  • Publication number: 20170288040
    Abstract: A method comprising: forming an SiGe layer on sidewalls of one or more fins of a semiconductor device by a non-selective deposition of amorphous SiGe, the fins being formed of Si or SiGe; depositing a silicon oxide layer over the SiGe layer; and forming an SiGe channel formation region within each fin by performing Ge enrichment to diffuse Ge atoms from the SiGe layer into the one or more fins.
    Type: Application
    Filed: April 1, 2016
    Publication date: October 5, 2017
    Applicants: Commissariat à l'Énergie Atomique et aux Énergies Alternatives, STMicroelectronics, Inc., International Business Machines Corporation
    Inventors: Emmanuel Augendre, Qing Liu, Rajasekhar Venigalla