Patents by Inventor Emmanuel Augendre

Emmanuel Augendre has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170263495
    Abstract: The method of manufacturing a structure comprising one or several strained semiconducting zones capable of forming one or several transistor channel regions, the method including the following steps: a) providing a substrate coated with a masking layer wherein there are one or several first slits exposing one or several first oblong semiconducting portions made of a first semiconducting material and extending in a first direction, b) making a second semiconducting material grow with a mesh parameter different from the mesh parameter of the first semiconducting material, so as to form one or several first semiconducting blocks strained along the first direction, on said one or several first oblong semiconducting portions.
    Type: Application
    Filed: March 13, 2017
    Publication date: September 14, 2017
    Applicants: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, STMICROELECTRONICS Inc
    Inventors: Emmanuel AUGENDRE, Nicolas LOUBET, Sylvain MAITREJEAN, Pierre MORIN
  • Publication number: 20170263607
    Abstract: Manufacture of a transistor device with at least one P type transistor with channel structure strained in uniaxial compression strain starting from a silicon layer strained in biaxial tension, by amorphisation recrystallisation then germanium condensation.
    Type: Application
    Filed: March 7, 2017
    Publication date: September 14, 2017
    Applicants: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, STMICROELECTRONICS Inc
    Inventors: Sylvain MAITREJEAN, Emmanuel Augendre, Pierre Morin, Shay Reboh
  • Patent number: 9704709
    Abstract: A Method for producing a layer of strained semiconductor material, the method comprising steps for: a) formation on a substrate of a stack comprising a first semiconductor layer based on a first semiconductor material coated with a second semiconductor layer based on a second semiconductor material having a different lattice parameter to that of the first semiconductor material, b) producing on the second semiconductor layer a mask having a symmetry, c) rendering amorphous the first semiconductor layer along with zones of the second semiconductor layer without rendering amorphous one or a plurality of regions of the second semiconductor layer protected by the mask and arranged respectively opposite the masking block(s), d) performing recrystallization of the regions rendered amorphous and the first semiconductor layer resulting in this first semiconductor layer being strained (FIG. 1A).
    Type: Grant
    Filed: September 9, 2016
    Date of Patent: July 11, 2017
    Assignees: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, STMicroelectronics (Crolles 2) SAS
    Inventors: Emmanuel Augendre, Aomar Halimaoui, Sylvain Maitrejean, Shay Reboh
  • Publication number: 20170141212
    Abstract: Method of making a transistor with semiconducting nanowires, including: making a semiconducting nanowire on a support, one portion of the nanowire being covered by a dummy gate, in which the dummy gate and the nanowire are surrounded by a dielectric layer, removing the dummy gate, forming a first space surrounded by first parts of the dielectric layer, making an ion implantation in a second part of the dielectric layer under said first portion, said first parts protecting third parts of the dielectric layer, etching said second part, forming a second space, making a gate in the spaces, and a dielectric portion on the gate and said first parts, making an ion implantation in fourth parts of the dielectric layer surrounding second portions of the nanowire, the dielectric portion protecting said first and third parts, etch said fourth parts.
    Type: Application
    Filed: November 15, 2016
    Publication date: May 18, 2017
    Applicant: Commissariat a L'Energie Atomique et aux Energies Alternatives
    Inventors: Sylvain BARRAUD, Emmanuel Augendre, Sylvain Maitrejean, Nicolas Posseme
  • Publication number: 20170076944
    Abstract: A Method for producing a layer of strained semiconductor material, the method comprising steps for: a) formation on a substrate of a stack comprising a first semiconductor layer based on a first semiconductor material coated with a second semiconductor layer based on a second semiconductor material having a different lattice parameter to that of the first semiconductor material, b) producing on the second semiconductor layer a mask having a symmetry, c) rendering amorphous the first semiconductor layer along with zones of the second semiconductor layer without rendering amorphous one or a plurality of regions of the second semiconductor layer protected by the mask and arranged respectively opposite the masking block(s) d) performing recrystallisation of the regions rendered amorphous and the first semiconductor layer resulting in this first semiconductor layer being strained (FIG. 1A).
    Type: Application
    Filed: September 9, 2016
    Publication date: March 16, 2017
    Applicants: Commissariat a L'Energie Atomique et aux Energies Alternatives, STMicroelectronics (Crolles 2) SAS
    Inventors: Emmanuel AUGENDRE, Aomar Halimaoui, Sylvain Maitrejean, Shay Reboh
  • Patent number: 9536951
    Abstract: FinFET transistor comprising at least: one fin that forms a channel, a source and a drain, comprising an alternating stack of first portions of silicon-rich SiGe and of second portions of a dielectric or semiconductor material, and third portions of germanium-rich SiGe arranged at least against lateral faces of the first portions, one gate that covers the channel, and wherein each one of the third portions comprises faces with a crystal orientation [111] covered by the gate.
    Type: Grant
    Filed: September 9, 2015
    Date of Patent: January 3, 2017
    Assignee: Commissariat à l'énergie atomique et aux énergies alternatives
    Inventors: Sylvain Maitrejean, Emmanuel Augendre, Louis Hutin, Yves Morand
  • Publication number: 20160372362
    Abstract: A method of transferring a thin layer from a first substrate to a second substrate with different coefficients of thermal expansion, including: providing at least one intermediate layer which temperature is increased by induction when an electromagnetic field is applied to it, more than a temperature increase in the first and second substrates; making contact between the first substrate and the second substrate, with the at least one intermediate layer interposed between them; fracturing the first substrate at a weakened zone making use of supply of thermal energy at the weakened zone made by applying an electromagnetic field to a heterostructure formed by making contact between the first substrate and the second substrate, the application generating local induction heating in the intermediate layer that induces a temperature gradient with a local value at the weakened zone activating the fracture mechanism.
    Type: Application
    Filed: June 27, 2014
    Publication date: December 22, 2016
    Applicant: Commissariat a l'energie atomique et aux energies alternatives
    Inventors: Thomas SIGNAMARCHEIX, Emmanuel AUGENDRE, Lamine BENAISSA
  • Publication number: 20160254362
    Abstract: A Method for modifying the strain state of a semiconducting structure, comprising steps to: a) provide at least one first semiconducting structure on a substrate, formed from a semiconducting stack comprising an alternation of elements based on the first semiconducting material and elements based on the second semiconducting material, then b) remove portions of the second semiconducting material from the first structure so as to form empty spaces, c) fill in the empty spaces with a dielectric material, d) form a straining zone on the first structure, based on a first strained material, e) perform appropriate thermal annealing so as to make the dielectric material creep or relax, and cause a change in the strain state of elements based on the first semiconducting material in the structure.
    Type: Application
    Filed: February 22, 2016
    Publication date: September 1, 2016
    Applicant: Commissariat a L'Energie Atomique et aux Energies Alternatives
    Inventors: Sylvain MAITREJEAN, Emmanuel AUGENDRE, Jean-Charles BARBE, Benoit MATHIEU, Yves MORAND
  • Publication number: 20160181439
    Abstract: A field-effect transistor including an active zone comprises a source, a channel, a drain and a control gate, which is positioned level with the channel, allowing a current to flow through the channel between the source and drain along an x-axis, the channel comprising: a first edge of separation with the source; and a second edge of separation with the drain; the channel being compressively or tensilely strained, wherein the channel includes a localized perforation or a set of localized perforations along at least the first and/or second edge of the channel so as to also create at least one shear strain in the channel. A process for fabricating the transistor is provided.
    Type: Application
    Filed: December 22, 2015
    Publication date: June 23, 2016
    Inventors: Emmanuel AUGENDRE, Maxime ARGOUD, Sylvain MAITREJEAN, Pierre MORIN, Raluca TIRON
  • Publication number: 20160071933
    Abstract: FinFET transistor comprising at least: one fin that forms a channel, a source and a drain, comprising an alternating stack of first portions of silicon-rich SiGe and of second portions of a dielectric or semiconductor material, and third portions of germanium-rich SiGe arranged at least against lateral faces of the first portions, one gate that covers the channel, and wherein each one of the third portions comprises faces with a crystal orientation [111] covered by the gate.
    Type: Application
    Filed: September 9, 2015
    Publication date: March 10, 2016
    Applicant: Commissariat A L'Energie Atomique et aux Energies Alternatives
    Inventors: Sylvain MAITREJEAN, Emmanuel AUGENDRE, Louis HUTIN, Yves MORAND
  • Publication number: 20150380491
    Abstract: A crystalline layer is produced from a crystalline substrate made from a first material on which a masking layer has previously been deposited; the masking layer containing at least one trench forming an access to the substrate, by: forming a crystalline buffer layer situated at least partly in the trench in the masking layer, extending from the substrate and forming a projection beyond the masking layer so that an upper part of the lateral flanks of said buffer layer is left uncovered, the formation step comprising a growth of the buffer layer from the substrate, and forming a crystalline epitaxial layer in a second material, different from the material of the buffer layer, by growth from said upper part of the lateral flanks of the buffer layer left uncovered.
    Type: Application
    Filed: June 29, 2015
    Publication date: December 31, 2015
    Applicant: Commissariat A L'Energie Atomique et aux Energies Alternatives
    Inventors: Emmanuel AUGENDRE, Thierry Baron
  • Publication number: 20150180038
    Abstract: The present invention relates to a bipolar battery comprising at least two electrochemical cells (C1, C2) stacked on top of one another, each collector (13, 21) comprising on its periphery at least one bead (23) of an electrically insulating material also forming a peripheral zone of the wall impermeable to the electrolyte. According to the invention, each impermeable wall is obtained by a technique chosen from direct bonding, anodic bonding between a bead of the bipolar collector and the bead of the adjacent collector, and eutectic bonding between a layer made of metal or a eutectic metal alloy deposited on a bead of the bipolar collector and a layer made of metal or eutectic metal alloy deposited on a bead of the adjacent collector.
    Type: Application
    Filed: July 3, 2013
    Publication date: June 25, 2015
    Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Jean-Francois Damlencourt, Emmanuel Augendre, Frank Fournel
  • Patent number: 8853785
    Abstract: An integrated circuit including at least: a first MOS transistor; a second MOS transistor, arranged on the first MOS transistor, the second MOS transistor including a channel region in at least one semiconductor layer including two approximately parallel primary faces; a portion of at least one electrically conductive material electrically connected to a gate of the first transistor and arranged between the gate of the first transistor and the channel region of the second transistor; a dielectric layer arranged at least between the portion of the electrically conductive material and the channel region of the second transistor; and a section of the channel region of the second transistor in a plane parallel to the two primary faces of the semiconductor layer is included in a section of the portion of the electrically conductive material projected in said plane.
    Type: Grant
    Filed: August 25, 2010
    Date of Patent: October 7, 2014
    Assignee: Commissariat a l'Energie Atomique et aux Energies Alternatives
    Inventors: Emmanuel Augendre, Maud Vinet, Laurent Clavelier, Perrine Batude
  • Patent number: 8809964
    Abstract: An electronic subassembly and associated method for the production of an electronic subassembly include a semiconductor layer bearing at least a first transistor having an adjustable threshold voltage is joined to an insulator layer and in which a first trapping zone is formed at a predetermined first depth. The first trapping zone extends at least beneath a channel of the first transistor and includes traps of greater density than the density of traps outside the first trapping zone, in such a way that the semiconductor layer and the first trapping zone are capacitively coupled. The useful information from the first transistor includes the charge transport within this transistor. A second trapping zone can be formed that extends at least beneath a channel of a second transistor that is formed by a second implantation with an energy and/or a dose and/or atoms that differ from those used to form the first trapping zone.
    Type: Grant
    Filed: February 11, 2009
    Date of Patent: August 19, 2014
    Assignee: Commissariat a l'Energie Atomique et Aux Energies Alternatives
    Inventors: François Andrieu, Emmanuel Augendre, Laurent Clavelier, Marek Kostrzewa
  • Publication number: 20110147849
    Abstract: An integrated circuit including: a first transistor; a second transistor, arranged on the first transistor, whereof a channel region is formed in a semiconductor layer including two approximately parallel primary faces; a portion of an electrically conductive material electrically connected to a gate of the first transistor and arranged between the gate of the first transistor and the channel region of the second transistor; a dielectric layer arranged between the portion of the electrically conductive material and the channel region of the second transistor; and in which the section of the channel region of the second transistor is included in the section of the portion of the electrically conductive material, and the channel region of the second transistor is arranged between the portion of the electrically conductive material and a gate of the second transistor.
    Type: Application
    Filed: August 25, 2010
    Publication date: June 23, 2011
    Applicant: COMMISS. A L'ENERGIE ATOM. ET AUX ENERG. ALTERNA.
    Inventors: Emmanuel AUGENDRE, Maud Vinet, Laurent Clavelier, Perrine Batude
  • Patent number: 7879690
    Abstract: A microstructure of the semiconductor on insulator type with different patterns is produced by forming a stacked uniform structure including a plate forming a substrate, a continuous insulative layer and a semiconductor layer. The continuous insulative layer is a stack of at least three elementary layers, including a bottom elementary layer, at least one intermediate elementary layer, and a top elementary layer overlying the semiconductor layer, where at least one of the bottom elementary layer and the top elementary layer being of an insulative material. In the stacked uniform structure, at least two patterns are differentiated by modifying at least one of the elementary layers in one of the patterns so that the elementary layer has a significantly different physical or chemical property between the two patterns, where at least one of the bottom and top elementary layer is an insulative material that remains unchanged.
    Type: Grant
    Filed: March 27, 2009
    Date of Patent: February 1, 2011
    Assignee: Commissariat a l'Energie Atomique
    Inventors: Emmanuel Augendre, Thomas Ernst, Marek Kostrzewa, Hubert Moriceau
  • Publication number: 20110001184
    Abstract: An electronic subassembly and associated method for the production of an electronic subassembly include a semiconductor layer bearing at least a first transistor having an adjustable threshold voltage is joined to an insulator layer and a in which a first trapping zone is formed at a predetermined first depth. The first trapping zone extends at least beneath a channel of the first transistor and includes traps of greater density than the density of traps outside the first trapping zone, in such a way that the semiconductor layer and the first trapping zone are capacitively coupled. The useful information from the first transistor includes the charge transport within this transistor. A second trapping zone can be formed that extends at least beneath a channel of a second transistor that is formed by a second implantation with an energy and/or a dose and/or atoms that differ from those used to form the first trapping zone.
    Type: Application
    Filed: February 11, 2009
    Publication date: January 6, 2011
    Inventors: Francois Andrieu, Emmanuel Augendre, Laurent Clavelier, Marek Kostrzewa
  • Publication number: 20090246946
    Abstract: A microstructure of the semiconductor on insulator type with different patterns is produced by forming a stacked uniform structure including a plate forming a substrate, a continuous insulative layer and a semiconductor layer. The continuous insulative layer is a stack of at least three elementary layers, including a bottom elementary layer, at least one intermediate elementary layer, and a top elementary layer overlying the semiconductor layer, where at least one of the bottom elementary layer and the top elementary layer being of an insulative material. In the stacked uniform structure, at least two patterns are differentiated by modifying at least one of the elementary layers in one of the patterns so that the elementary layer has a significantly different physical or chemical property between the two patterns, where at least one of the bottom and top elementary layer is an insulative material that remains unchanged.
    Type: Application
    Filed: March 27, 2009
    Publication date: October 1, 2009
    Inventors: Emmanuel Augendre, Thomas Ernst, Marek Kostrzewa, Hubert Moriceau
  • Patent number: 6855605
    Abstract: A method of forming layers, in the same device material, with different thickness or layer height in a semiconductor device comprises forming device material layer or gate electrode layer disposable parts in selected regions of the device layer. The disposable parts can be formed by doping the selected regions to the desired depth d. The as-deposited thickness t of this device layer can be adjusted or modulated after the patterning of the individual devices by removing the disposable parts.
    Type: Grant
    Filed: October 30, 2002
    Date of Patent: February 15, 2005
    Assignee: Interuniversitair Microelektronica Centrum (IMEC)
    Inventors: Malgorzata Jurczak, Rita Rooyackers, Emmanuel Augendre, Goncal Badenes
  • Publication number: 20030099766
    Abstract: A method of forming layers, in the same device material, with different thickness or layer height in a semiconductor device comprises forming device material layer or gate electrode layer disposable parts in selected regions of the device layer. The disposable parts can be formed by doping the selected regions to the desired depth d. The as-deposited thickness t of this device layer can be adjusted or modulated after the patterning of the individual devices by removing the disposable parts.
    Type: Application
    Filed: October 30, 2002
    Publication date: May 29, 2003
    Inventors: Malgorzata Jurczak, Rita Rooyackers, Emmanuel Augendre, Goncal Badenes