Patents by Inventor Emmanuelle Marie Josèphe Janz

Emmanuelle Marie Josèphe Janz has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9716621
    Abstract: A programmable transceiver for a network element includes a programmable circuit including internal logic and control logic. Interfaces connect the programmable circuit to a network and a network element. The control logic facilitates programming of the internal logic responsive to an in-band program signal while the programmable circuit services network traffic received via at least one of the interfaces.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: July 25, 2017
    Assignee: VIAVI SOLUTIONS INC.
    Inventors: Emmanuelle Marie Josèphe Janz, Luc Chouinard, David George Coomber
  • Patent number: 9438503
    Abstract: The disclosure relates to test-capable pluggable transceivers and network systems and methods using such transceivers. A central test server generates a test request and communicates to a mediation sub-system, which uses a common management protocol to communicate with a plurality of transceivers in the network. The mediation sub-system translates the test request into sub-tests and generates sequences of test-control commands for executing by specific transceivers to configure test logic deployed within the transceivers for testing designated network services, to generate test frames, and/or to process received frames to collect test results.
    Type: Grant
    Filed: September 19, 2013
    Date of Patent: September 6, 2016
    Assignee: VIAVI SOLUTIONS INC.
    Inventors: David George Coomber, Emmanuelle Marie Josèphe Janz, Jason Curry
  • Publication number: 20160020948
    Abstract: A programmable transceiver for a network element includes a programmable circuit including internal logic and control logic. Interfaces connect the programmable circuit to a network and a network element. The control logic facilitates programming of the internal logic responsive to an in-band program signal while the programmable circuit services network traffic received via at least one of the interfaces.
    Type: Application
    Filed: September 25, 2015
    Publication date: January 21, 2016
    Applicant: JDS Uniphase Corporation
    Inventors: Emmanuelle Marie Josèphe JANZ, Luc CHOUINARD, David George COOMBER
  • Patent number: 9148341
    Abstract: Devices and methods for partially upgrading a programmable pluggable transceiver that is in service using the regular datapaths without degrading the basic transparent, hitless pass-through functionality of the transceiver. The programmable logic gate array can be divided into four generalized parts: core logic for basic transceiver pass-through functionality over the datapaths, upgradeable internal logic, connectivity logic for selectively outputting on the datapaths from the core and internal logics, and control logic for isolating, upgrading and reconnecting the internal logic without affecting the basic transparent hitless pass-through functionality of the transceiver.
    Type: Grant
    Filed: March 26, 2013
    Date of Patent: September 29, 2015
    Assignee: JDS UNIPHASE CORPORATION
    Inventors: Emmanuelle Marie Josèphe Janz, Luc Chouinard, David George Coomber
  • Patent number: 9118601
    Abstract: A pluggable transceiver, and its use, looping back Layer 2 and higher data in an Ethernet network element. The transceiver has upstream and downstream datapaths, a logic array having first and second complimentary latching loopback logic blocks (LLBLBs) connected in series through both datapaths. The first LLBLB receiving an upstream datapath frame, comparing it to loopback conditions and looping back the frame on the downstream datapath if the conditions match. If the conditions did not match, the frame is sent to the other LLBLB. The first LLBLB receiving a frame from the second LLB and transmitting it on the upstream datapath with priority over any loop back frames to maintain the upstream throughput requirements of the pluggable transceiver. The second LLBLB operates in mirror image with respect to the datapaths.
    Type: Grant
    Filed: March 4, 2013
    Date of Patent: August 25, 2015
    Assignee: JDS Uniphase Corporation
    Inventors: Luc Chouinard, David George Coomber, Richard Charles Vieregge, Emmanuelle Marie Josèphe Janz
  • Publication number: 20140016479
    Abstract: The disclosure relates to test-capable pluggable transceivers and network systems and methods using such transceivers. A central test server generates a test request and communicates to a mediation sub-system, which uses a common management protocol to communicate with a plurality of transceivers in the network. The mediation sub-system translates the test request into sub-tests and generates sequences of test-control commands for executing by specific transceivers to configure test logic deployed within the transceivers for testing designated network services, to generate test frames, and/or to process received frames to collect test results.
    Type: Application
    Filed: September 19, 2013
    Publication date: January 16, 2014
    Inventors: David George COOMBER, Luc CHOUINARD, Emmanuelle Marie Josèphe JANZ, Jason CURRY
  • Publication number: 20130250813
    Abstract: Devices and methods for partially upgrading a programmable pluggable transceiver that is in service using the regular datapaths without degrading the basic transparent, hitless pass-through functionality of the transceiver. The programmable logic gate array can be divided into four generalized parts: core logic for basic transceiver pass-through functionality over the datapaths, upgradeable internal logic, connectivity logic for selectively outputting on the datapaths from the core and internal logics, and control logic for isolating, upgrading and reconnecting the internal logic without affecting the basic transparent hitless pass-through functionality of the transceiver.
    Type: Application
    Filed: March 26, 2013
    Publication date: September 26, 2013
    Inventors: Emmanuelle Marie Josèphe JANZ, Luc CHOUINARD, David George COOMBER
  • Publication number: 20130229927
    Abstract: A pluggable transceiver, and its use, looping back Layer 2 and higher data in an Ethernet network element. The transceiver has upstream and downstream datapaths, a logic array having first and second complimentary latching loopback logic blocks (LLBLBs) connected in series through both datapaths. The first LLBLB receiving an upstream datapath frame, comparing it to loopback conditions and looping back the frame on the downstream datapath if the conditions match. If the conditions did not match, the frame is sent to the other LLBLB. The first LLBLB receiving a frame from the second LLB and transmitting it on the upstream datapath with priority over any loop back frames to maintain the upstream throughput requirements of the pluggable transceiver. The second LLBLB operates in mirror image with respect to the datapaths.
    Type: Application
    Filed: March 4, 2013
    Publication date: September 5, 2013
    Inventors: Luc Chouinard, David George Coomber, Richard Charles Vieregge, Emmanuelle Marie Josèphe Janz