Patents by Inventor Emre Alptekin

Emre Alptekin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10818759
    Abstract: A fin-shaped field effect transistor (finFET) device comprising includes a substrate. an insulating layer displaced over the substrate, and a fin. The device also includes a gate formed over the fin, the gate including: a gate stack; and a high-k dielectric on opposing side of the gate stack. The device further includes metallic source and drain regions formed over the fin and on opposing sides of the gate.
    Type: Grant
    Filed: July 2, 2019
    Date of Patent: October 27, 2020
    Assignee: Tessera, Inc.
    Inventors: Emre Alptekin, Robert R. Robison, Reinaldo A. Vega
  • Publication number: 20200328205
    Abstract: In an embodiment, an integrated circuit includes transistors in different active regions, electrically isolated using single diffusion break isolation. The single diffusion break isolation includes a first dummy transistor that has a different threshold voltage than the transistors in either active region for which the single diffusion break is creating isolation. The first dummy transistor may have lower leakage current than transistors in either active region, creating effective isolation between the active regions and consuming relatively small amounts of power due to the lower leakage currents.
    Type: Application
    Filed: June 26, 2020
    Publication date: October 15, 2020
    Inventors: Emre Alptekin, Thomas Hoffmann
  • Patent number: 10707167
    Abstract: An aspect of the invention includes a method for forming a contact in a dielectric layer over a semiconductor substrate. The method may comprise: forming a contact opening in a dielectric layer over the semiconductor substrate to expose an upper portion of the semiconductor substrate; depositing a first liner layer to conformally coat the contact opening; causing a portion of the first liner layer to diffuse into the upper portion of the semiconductor substrate to form a first intermix region at the upper portion of the semiconductor substrate; depositing a refractory metal layer over the first intermix region; and depositing a metal in the contact opening thereby forming the contact.
    Type: Grant
    Filed: November 30, 2017
    Date of Patent: July 7, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Emre Alptekin, Nicolas L. Breil, Christian Lavoie, Ahmet S. Ozcan, Kathryn T. Schonenberg
  • Patent number: 10700065
    Abstract: In an embodiment, an integrated circuit includes transistors in different active regions, electrically isolated using single diffusion break isolation. The single diffusion break isolation includes a first dummy transistor that has a different threshold voltage than the transistors in either active region for which the single diffusion break is creating isolation. The first dummy transistor may have lower leakage current than transistors in either active region, creating effective isolation between the active regions and consuming relatively small amounts of power due to the lower leakage currents.
    Type: Grant
    Filed: October 10, 2018
    Date of Patent: June 30, 2020
    Assignee: Apple Inc.
    Inventors: Emre Alptekin, Thomas Hoffmann
  • Patent number: 10693005
    Abstract: A method for manufacturing a semiconductor device comprises forming a plurality of fins in an active region, forming a plurality of gates around the plurality of fins in the active region, forming one or more gate contacts in the active region, and forming a plurality of contacts to source/drain regions in the active region.
    Type: Grant
    Filed: April 30, 2019
    Date of Patent: June 23, 2020
    Assignee: International Business Machines Corporation
    Inventors: Emre Alptekin, Albert M. Chu, Eric Eastman, Myung-Hee Na, Ravikumar Ramachandran
  • Publication number: 20200118999
    Abstract: In an embodiment, an integrated circuit includes transistors in different active regions, electrically isolated using single diffusion break isolation. The single diffusion break isolation includes a first dummy transistor that has a different threshold voltage than the transistors in either active region for which the single diffusion break is creating isolation. The first dummy transistor may have lower leakage current than transistors in either active region, creating effective isolation between the active regions and consuming relatively small amounts of power due to the lower leakage currents.
    Type: Application
    Filed: October 10, 2018
    Publication date: April 16, 2020
    Inventors: Emre Alptekin, Thomas Hoffmann
  • Publication number: 20200058758
    Abstract: A method for forming a salicide includes forming, on at least one semiconductor fin, at least one source/drain (S/D) region including a (111) facet and having a cross-sectional quadrilateral shape, forming a conductive material on the (111) facet, annealing the conductive material to form a silicide on the (111) facet, and forming at least one contact to the silicide.
    Type: Application
    Filed: October 24, 2019
    Publication date: February 20, 2020
    Inventors: Praneet Adusumilli, Emre Alptekin, Christian Lavoie, Ahmet S. Ozcan
  • Patent number: 10546941
    Abstract: A method for forming a salicide includes epitaxially growing source/drain (S/D) regions on a semiconductor fin wherein the S/D regions include (111) facets in a diamond shape and the S/D regions on adjacent fins have separated diamond shapes. A metal is deposited on the (111) facets. A thermally stabilizing anneal process is performed to anneal the metal on the S/D regions to form a silicide on the (111) facets. A dielectric layer is formed over the S/D regions. The dielectric layer is opened up to expose the silicide and to form contact holes. Contacts to the silicide are formed in the contact holes.
    Type: Grant
    Filed: November 8, 2017
    Date of Patent: January 28, 2020
    Assignee: International Business Machines Corporation
    Inventors: Praneet Adusumilli, Emre Alptekin, Christian Lavoie, Ahmet S. Ozcan
  • Publication number: 20190348519
    Abstract: A semiconductor device includes epitaxially grown source/drain (S/D) regions each having a cross-sectional quadrilateral shape formed on a semiconductor fin on opposite sides of a transversely disposed gate structure. The S/D regions include top (111) facets on top halves of the cross-sectional quadrilateral shape. The device further includes a silicide formed on the top (111) facets.
    Type: Application
    Filed: July 29, 2019
    Publication date: November 14, 2019
    Inventors: Praneet Adusumilli, Emre Alptekin, Christian Lavoie, Ahmet S. Ozcan
  • Publication number: 20190326406
    Abstract: A fin-shaped field effect transistor (finFET) device comprising includes a substrate. an insulating layer displaced over the substrate, and a fin. The device also includes a gate formed over the fin, the gate including: a gate stack; and a high-k dielectric on opposing side of the gate stack. The device further includes metallic source and drain regions formed over the fin and on opposing sides of the gate.
    Type: Application
    Filed: July 2, 2019
    Publication date: October 24, 2019
    Inventors: Emre Alptekin, Robert R. Robison, Reinaldo A. Vega
  • Patent number: 10453935
    Abstract: A method for forming a salicide includes epitaxially growing source/drain (S/D) regions on a semiconductor fin wherein the S/D regions include (111) facets in a diamond shape and the S/D regions on adjacent fins have separated diamond shapes. A metal is deposited on the (111) facets. A thermally stabilizing anneal process is performed to anneal the metal on the S/D regions to form a silicide on the (111) facets. A dielectric layer is formed over the S/D regions. The dielectric layer is opened up to expose the silicide and to form contact holes. Contacts to the silicide are formed in the contact holes.
    Type: Grant
    Filed: April 20, 2017
    Date of Patent: October 22, 2019
    Assignee: International Business Machines Corporation
    Inventors: Praneet Adusumilli, Emre Alptekin, Christian Lavoie, Ahmet S. Ozcan
  • Patent number: 10418450
    Abstract: A fin-shaped field effect transistor (finFET) device comprising includes a substrate, an insulating layer displaced over the substrate, and a fin. The device also includes a gate formed over the fin, the gate including: a gate stack; and a high-k dielectric on opposing side of the gate stack. The device further includes metallic source and drain regions formed over the fin and on opposing sides of the gate.
    Type: Grant
    Filed: April 22, 2016
    Date of Patent: September 17, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Emre Alptekin, Robert R. Robison, Reinaldo A Vega
  • Publication number: 20190259869
    Abstract: A method for manufacturing a semiconductor device comprises forming a plurality of fins in an active region, forming a plurality of gates around the plurality of fins in the active region, forming one or more gate contacts in the active region, and forming a plurality of contacts to source/drain regions in the active region.
    Type: Application
    Filed: April 30, 2019
    Publication date: August 22, 2019
    Inventors: Emre Alptekin, Albert M. Chu, Eric Eastman, Myung-Hee Na, Ravikumar Ramachandran
  • Publication number: 20190259852
    Abstract: A method of fabricating a finFET semiconductor device, the method including forming a self-aligned silicide contact above and in direct contact with exposed portions of semiconductor fins not covered by a gate electrode, wherein an upper surface of the self-aligned silicide contact is substantially flush with an upper surface of an adjacent isolation region, patterning a blanket metal layer to form a source-drain contact on the upper surface of the self-aligned silicide contact, the self-aligned silicide contact provides an electrical path from the semiconductor fins to the source-drain contact, and recessing a portion of the self-aligned silicide contact without recessing the isolation region, the self-aligned silicide contact is recessed selective to a mask used to pattern the source-drain contact.
    Type: Application
    Filed: May 3, 2019
    Publication date: August 22, 2019
    Inventors: Emre Alptekin, Veeraraghavan S. Basker, Sivananda K. Kanakasabapathy
  • Patent number: 10381480
    Abstract: A method for manufacturing a semiconductor device comprises forming a plurality of fins in an active region, forming a plurality of gates around the plurality of fins in the active region, forming one or more gate contacts in the active region, and forming a plurality of contacts to source/drain regions in the active region.
    Type: Grant
    Filed: September 27, 2017
    Date of Patent: August 13, 2019
    Assignee: International Business Machines Corporation
    Inventors: Emre Alptekin, Albert M. Chu, Eric Eastman, Myung-Hee Na, Ravikumar Ramachandran
  • Patent number: 10326000
    Abstract: A method of fabricating a finFET semiconductor device, the method including forming a self-aligned silicide contact above and in direct contact with exposed portions of semiconductor fins not covered by a gate electrode, wherein an upper surface of the self-aligned silicide contact is substantially flush with an upper surface of an adjacent isolation region, patterning a blanket metal layer to form a source-drain contact on the upper surface of the self-aligned silicide contact, the self-aligned silicide contact provides an electrical path from the semiconductor fins to the source-drain contact, and recessing a portion of the self-aligned silicide contact without recessing the isolation region, the self-aligned silicide contact is recessed selective to a mask used to pattern the source-drain contact.
    Type: Grant
    Filed: January 24, 2018
    Date of Patent: June 18, 2019
    Assignee: International Business Machines Corporation
    Inventors: Emre Alptekin, Veeraraghavan S. Basker, Sivananda K. Kanakasabapathy
  • Publication number: 20190097016
    Abstract: A method for manufacturing a semiconductor device comprises forming a plurality of fins in an active region, forming a plurality of gates around the plurality of fins in the active region, forming one or more gate contacts in the active region, and forming a plurality of contacts to source/drain regions in the active region.
    Type: Application
    Filed: September 27, 2017
    Publication date: March 28, 2019
    Inventors: Emre Alptekin, Albert M. Chu, Eric Eastman, Myung-Hee Na, Ravikumar Ramachandran
  • Patent number: 10236344
    Abstract: A tunnel field effect transistor (TFET) including a first doped source region for a first type TFET or a second doped source region for a second type TFET; a second doped drain region for the first type TFET or a first doped drain region for the second type TFET; a body region that is either intrinsic or doped, with a doping concentration less than that of the first or second source region, separating the first or second source from the first or second drain regions; a self-aligned etch cavity separating the first or second doped source and drain regions; a thin epitaxial channel region that is grown within the self-aligned etch cavity, covering at least the first or the second source region; a replacement gate stack comprising a high-k gate dielectric and one or a combination of metals and polysilicon; and sidewall spacers adjacent to the replacement gate stack.
    Type: Grant
    Filed: October 20, 2015
    Date of Patent: March 19, 2019
    Assignee: International Business Machines Corporation
    Inventors: Emre Alptekin, Hung H. Tran, Reinaldo A. Vega, Xiaobin Yuan
  • Patent number: 10170581
    Abstract: A method of fabricating a finFET semiconductor device, the method including forming a self-aligned silicide contact above and in direct contact with exposed portions of semiconductor fins not covered by a gate electrode, wherein an upper surface of the self-aligned silicide contact is substantially flush with an upper surface of an adjacent isolation region, patterning a blanket metal layer to form a source-drain contact on the upper surface of the self-aligned silicide contact, the self-aligned silicide contact provides an electrical path from the semiconductor fins to the source-drain contact, and recessing a portion of the self-aligned silicide contact without recessing the isolation region, the self-aligned silicide contact is recessed selective to a mask used to pattern the source-drain contact.
    Type: Grant
    Filed: December 26, 2017
    Date of Patent: January 1, 2019
    Assignee: International Business Machines Corporation
    Inventors: Emre Alptekin, Veeraraghavan S. Basker, Sivananda K. Kanakasabapathy
  • Patent number: 10121789
    Abstract: A semiconductor substrate includes lower source/drain (S/D) regions. A replacement metal gate (RMG) structure is arranged upon the semiconductor substrate between the lower S/D regions. Raised S/D regions are arranged upon the lower S/D regions adjacent to the RMG structure, respectively. The raised S/D regions may be recessed to form contact trenches. First self-aligned contacts are located upon the raised S/D regions within a first active area and second self-aligned contacts are located upon the recessed raised S/D regions in the second active area. The first and second self-aligned contacts allows for independent reduction of source drain contact resistances. The first self-aligned contacts may be MIS contacts or metal silicide contacts and the second self-aligned contacts may be metal-silicide contacts.
    Type: Grant
    Filed: January 3, 2017
    Date of Patent: November 6, 2018
    Assignee: International Business Machines Corporation
    Inventors: Praneet Adusumilli, Emre Alptekin, Kangguo Cheng, Balasubramanian Pranatharthiharan, Shom S. Ponoth