Patents by Inventor Eri Matsuo

Eri Matsuo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11127762
    Abstract: A semiconductor device includes a semiconductor film, a semiconductor auxiliary film, a wiring line, a first metal film, and an interlayer insulating film. The semiconductor film includes a channel region and a low-resistance region. The semiconductor film includes indium and oxygen. The semiconductor auxiliary film is in contact with the low-resistance region of the semiconductor film and reduces the electric resistance of the semiconductor film. The wiring line is electrically coupled to the low-resistance region of the semiconductor film. The first metal film covers the wiring line and has a higher standard electrode potential than the indium. The interlayer insulating film covers the semiconductor film with the first metal film interposed therebetween. The interlayer insulating film has a first hole and a second hole. The first hole is provided at a position opposed to the low-resistance region of the semiconductor film. The second hole reaches the first metal film.
    Type: Grant
    Filed: July 22, 2019
    Date of Patent: September 21, 2021
    Assignee: JOLED INC.
    Inventors: Eri Matsuo, Yasuhiro Terai
  • Publication number: 20200266219
    Abstract: A semiconductor device includes a semiconductor film, a semiconductor auxiliary film, a wiring line, a first metal film, and an interlayer insulating film. The semiconductor film includes a channel region and a low-resistance region. The semiconductor film includes indium and oxygen. The semiconductor auxiliary film is in contact with the low-resistance region of the semiconductor film and reduces the electric resistance of the semiconductor film. The wiring line is electrically coupled to the low-resistance region of the semiconductor film. The first metal film covers the wiring line and has a higher standard electrode potential than the indium. The interlayer insulating film covers the semiconductor film with the first metal film interposed therebetween. The interlayer insulating film has a first hole and a second hole. The first hole is provided at a position opposed to the low-resistance region of the semiconductor film. The second hole reaches the first metal film.
    Type: Application
    Filed: July 22, 2019
    Publication date: August 20, 2020
    Inventors: Eri MATSUO, Yasuhiro TERAI
  • Patent number: 10551704
    Abstract: Provided is an active matrix substrate that includes a substrate, a thin film transistor, an electrode layer, and a second insulating film. The thin film transistor is provided on the substrate and includes an oxide semiconductor layer, a gate electrode, and source and drain electrodes. The oxide semiconductor layer includes a first region as a channel region. The electrode layer is level with the gate electrode, is provided in a different region from the thin film transistor, and includes a first end. The second insulating film is provided between the substrate and the electrode layer and includes a second end at a more retreated position than the first end of the electrode layer. The oxide semiconductor layer further includes a second region having lower resistance than the first region. The electrode layer is electrically coupled, at the first end, to the second region of the oxide semiconductor layer.
    Type: Grant
    Filed: June 7, 2017
    Date of Patent: February 4, 2020
    Assignee: JOLED INC.
    Inventors: Eri Matsuo, Tomoatsu Kinoshita, Motohiro Toyota, Yasunobu Hiromasu
  • Patent number: 10431603
    Abstract: A semiconductor device includes a substrate, a first wiring line, a semiconductor film, a second wiring line, and an insulating film. The substrate includes first, second, and third regions provided adjacently in this order in a predetermined direction. The first wiring line is provided on the substrate and provided in each of the first, second, and third regions. The semiconductor film has a low-resistance region in at least a portion thereof. The semiconductor film is provided between the first wiring line and the substrate in the first region, and is in contact with the first wiring line in the second region. The second wiring line is provided at a position closer to the substrate than the semiconductor film, and is in contact with the first wiring line in the third region. The insulating film is provided between the first wiring line and the semiconductor film in the first region.
    Type: Grant
    Filed: January 5, 2018
    Date of Patent: October 1, 2019
    Assignee: JOLED INC.
    Inventors: Hiroshi Hayashi, Tokuaki Kuniyoshi, Yasuhiro Terai, Eri Matsuo, Toshiaki Yoshitani, Naoki Asano
  • Publication number: 20180197884
    Abstract: A semiconductor device includes a substrate, a first wiring line, a semiconductor film, a second wiring line, and an insulating film. The substrate includes first, second, and third regions provided adjacently in this order in a predetermined direction. The first wiring line is provided on the substrate and provided in each of the first, second, and third regions. The semiconductor film has a low-resistance region in at least a portion thereof. The semiconductor film is provided between the first wiring line and the substrate in the first region, and is in contact with the first wiring line in the second region. The second wiring line is provided at a position closer to the substrate than the semiconductor film, and is in contact with the first wiring line in the third region. The insulating film is provided between the first wiring line and the semiconductor film in the first region.
    Type: Application
    Filed: January 5, 2018
    Publication date: July 12, 2018
    Inventors: Hiroshi HAYASHI, Tokuaki KUNIYOSHI, Yasuhiro TERAI, Eri MATSUO, Toshiaki YOSHITANI, Naoki ASANO
  • Publication number: 20170363926
    Abstract: Provided is an active matrix substrate that includes a substrate, a thin film transistor, an electrode layer, and a second insulating film. The thin film transistor is provided on the substrate and includes an oxide semiconductor layer, a gate electrode, and source and drain electrodes. The oxide semiconductor layer includes a first region as a channel region. The electrode layer is level with the gate electrode, is provided in a different region from the thin film transistor, and includes a first end. The second insulating film is provided between the substrate and the electrode layer and includes a second end at a more retreated position than the first end of the electrode layer. The oxide semiconductor layer further includes a second region having lower resistance than the first region. The electrode layer is electrically coupled, at the first end, to the second region of the oxide semiconductor layer.
    Type: Application
    Filed: June 7, 2017
    Publication date: December 21, 2017
    Inventors: Eri MATSUO, Tomoatsu KINOSHITA, Motohiro TOYOTA, Yasunobu HIROMASU
  • Patent number: 9246012
    Abstract: A display unit includes: an oxide semiconductor layer configured to form a channel; a first layer having electrical insulation or electrical conductivity; and a second layer including a hydrogen absorbent and disposed between the oxide semiconductor layer and the first layer.
    Type: Grant
    Filed: August 7, 2014
    Date of Patent: January 26, 2016
    Assignee: JOLED INC.
    Inventors: Shigehiro Yamakita, Eri Matsuo, Hiroshi Nishikawa, Kimihiro Shinya, Tomoatsu Kinoshita, Masanori Nishiyama, Kenichi Izumi
  • Publication number: 20150048361
    Abstract: A display unit includes: an oxide semiconductor layer configured to form a channel; a first layer having electrical insulation or electrical conductivity; and a second layer including a hydrogen absorbent and disposed between the oxide semiconductor layer and the first layer.
    Type: Application
    Filed: August 7, 2014
    Publication date: February 19, 2015
    Applicant: Sony Corporation
    Inventors: Shigehiro Yamakita, Eri Matsuo, Hiroshi Nishikawa, Kimihiro Shinya, Tomoatsu Kinoshita, Masanori Nishiyama, Kenichi Izumi