Abstract: The present invention provides a data processing apparatus and method for converting a number between fixed-point and floating-point representations. More particularly, the data processing apparatus comprises a data processing unit operable to execute instructions, with the data processing unit being responsive to a format conversion instruction to apply a format conversion operation to a number to perform a conversion between the fixed-point representation of the number and the floating-point representation of the number. Furthermore, a control field is provided which is arranged to provide a programmable value specifying a decimal point location within the fixed-point representation of the number, and the data processing unit is operable to reference the control field and to control the formal conversion operation in accordance with the programmable value.

Abstract: A static XOR gate is provided with circuit speeds necessary to meet the increasing demand of higher computer clock frequencies. The XOR of the present invention takes up less area and consumes less power than prior art XOR circuits. Furthermore, time XOR gate of the present invention is fully static and imposes less constraints on the circuit designer, e.g. no reset logic, input synchronization, or the like. The circuit utilizes only NMOS transistors in the functional logic portion with two output inverters. The circuit elements are symmetrical and have identical input loading, output drive and propagation paths. The XOR of the present invention allows multiple gates to be connected in stages as a "tree" configuration by providing a "push-pull" XOR/EQV (equivalent, i.e. time complement of the XOR output or XNOR) function which is buffered by output inverters to "push" the output to a next stage.

Abstract: This invention relates to personal computers, and more particularly to a personal computer system having an Input/Output (I/O) controller which imparts flexibility to the system design and operation. The I/O controller has a plurality of segments. A first segment provides a serial port for exchange of data signals; a second segment provides a parallel port for exchange of data signals; and a third segment provides a selectable interface for connection with a selected one of said option bus and said planar I/O bus. The third segment has a signal line for transmission of a feedback signal indicative of a readiness for transfer of data signals through one of said first and second segments.

Abstract: A system and method is provided which includes a set of N and P type transistors connected such that both positive active and negative dynamic logic input pulses may be received. The pulse catcher circuit of the present invention then outputs a static logic level based upon the input pulses. A first input circuit is included that receives the data signal and outputs a level (voltage or absence of a voltage) to an output invertor circuit which is used in conjunction with a feedback circuit as a latch to maintain the output at the desired level. The feedback circuit ensures that the level will be maintained in a stable state (i.e. ground potential for a logical "0" and Vdd for a logical "1"). In this manner the static logic levels output from the circuit will be maintained until another dynamic pulse is received. Additionally, the pulse catcher circuit will always provide a consistent static logic output, even when both of the dynamic logic input signals are in their active states.

Abstract: This invention relates to personal computers, and more particularly to a personal computer system having a signal passing component operatively connected for exchange of data signals with system components operatively connected with a local processor bus and having a segment providing a state machine for receiving external command signals passed on one of the system busses and for passing internal command signals identifying valid data intervals, said state machine requiring a predetermined minimum length of external command signal for issuance of an internal command signal and terminating an internal command signal with termination of an external command signal so as to avoid the adverse effects of crosstalk and transmission line noise on external commands signals and loss of data integrity thereby possibly occurring.