Abstract: Apparatus for optimizing low-density parity check (“LDPC”) decoding in a processor is disclosed herein. A processor in accordance with the present disclosure includes an LDPC decoder row update execution unit. The LDPC decoder row update execution unit accelerates an LDPC row update computation by performing a logarithm estimation and a magnitude minimization in parallel. The execution unit is activated by execution of an LDPC row update instruction. The execution unit adds a minimum of magnitudes of two input values to a difference of estimated logarithms of exponential functions of a sum and a difference of the two input values to produce a row update value.

Abstract: A digital signal processor for decoding Trellis based channel encoding stages based on radix-4 stages comprising means for rearranging the input and output data in Radix-4 Viterbi decoding to make inter-stage Trellis data movement suitable for use in the digital signal processor.

Abstract: A high data width accelerator, comprising computer instructions for calculating at least a portion of a trace-back during a trellis computation, wherein the calculation allows faster trace-back

Abstract: A digital signal processor (DSP) co-processor according to a clustered architecture with local memories. Each cluster in the architecture includes multiple sub-clusters, each sub-cluster capable of executing one or two instructions that may be specifically directed to a particular DSP operation. The sub-clusters in each cluster communicate with global memory resources by way of a crossbar switch in the cluster. One or more of the sub-clusters has a dedicated local memory that can be accessed in a random access manner, in a vector access manner, or in a streaming or stack manner. The local memory is arranged as a plurality of banks. In response to certain vector access instructions, the input data may be permuted among the banks prior to a write, or permuted after being read from the banks, according to a permutation pattern stored in a register.

Abstract: A co-processor for efficiently decoding codewords encoded according to a Low Density Parity Check (LDPC) code, and arranged to efficiently execute an instruction to multiply the value of one operand with the sign of another operand, is disclosed. Logic circuitry is included in the co-processor to select between the value of a second operand, and an arithmetic inverse of the second operand value, in response to the sign bit of the first operand. This logic circuitry is arranged to operate according to 2's-complement integer arithmetic, by also including invert-and-increment circuitry to produce a 2's-complement inverse of the second operand. A comparator determines whether the second operand is at a maximum 2's-complement negative value, in which case the arithmetic inverse is selected to be a hard-wired maximum 2's-complement positive value.

Abstract: Apparatus and method for optimizing interpolation in the despreader data-path of a wireless telecommunications network employing CDMA technology. A base station dynamically evaluates its configuration to determine an interpolator location. The location of the interpolator in a despreader data-path is dynamically selected. A received signal is interpolated. The despread received signals are combined, and further processing is applied to the combined signal. To enhance system performance, the interpolator may be located at least to perform chip-sample interpolation per antenna stream at chip rate, chip-sample interpolation per user at chip rate, or symbol-sample interpolation per user at (sub) symbol rate.

Abstract: A wireless communication system (10). The system comprises a transceiver (20), and the transceiver comprises a code counter (LCSTC 22c) and a clock oscillator (26) for advancing a count in the code counter. The transceiver further comprises circuitry (30) for receiving a time message based on a system time external from the transceiver and circuitry (28) for determining a system time count and for storing the system time count to the code counter in response to the time message. Further, code counter continues to be advanced from the system time count in response to the clock oscillator. The transceiver further comprises circuitry (28) for repeatedly evaluating the count in the code counter, after advancement from the system time count, to ascertain whether the count has drifted to an inaccurate count. Lastly, the transceiver further comprises circuitry (28), responsive to detecting an inaccurate count, for adjusting the inaccurate count to a perceived accurate count.

Abstract: A wireless base station (20). The base station comprises at least one receive antenna (ATRXn) for receiving communication signals from at least one transmitting station (UST), and the signals are spread with a plurality of chips. The base station further comprises circuitry (52) for selecting a set of chips corresponding to a first signal received by the at least one receive antenna and circuitry (60) for forming a set of de-spread chips corresponding to the set of chips and in response to a code. Still further, the base station comprises a functional data path (56) comprising an accumulator for receiving the set of de-spread chips and circuitry for receiving an instruction. The functional data path is operable in response to a first instruction, received by the circuitry for receiving an instruction, to accumulate (621 or 622) a first number of de-spread chips in the set of de-spread chips for producing at least one corresponding symbol.

Abstract: A wireless communication system (10). The system comprises a transceiver (20), and the transceiver comprises a code counter (LCSTC 22c) and a clock oscillator (26) for advancing a count in the code counter. The transceiver further comprises circuitry (30) for receiving a time message based on a system time external from the transceiver and circuitry (28) for determining a system time count and for storing the system time count to the code counter in response to the time message. Further, code counter continues to be advanced from the system time count in response to the clock oscillator. The transceiver further comprises circuitry (28) for repeatedly evaluating the count in the code counter, after advancement from the system time count, to ascertain whether the count has drifted to an inaccurate count. Lastly, the transceiver further comprises circuitry (28), responsive to detecting an inaccurate count, for adjusting the inaccurate count to a perceived accurate count.

Abstract: A wireless base station (20). The base station comprises at least one receive antenna (ATRXn) for receiving communication signals from at least one transmitting station (UST), and the signals are spread with a plurality of chips. The base station further comprises circuitry (52) for selecting a set of chips corresponding to a first signal received by the at least one receive antenna and circuitry (60) for forming a set of de-spread chips corresponding to the set of chips and in response to a code. Still further, the base station comprises a functional data path (56) comprising an accumulator for receiving the set of de-spread chips and circuitry for receiving an instruction. The functional data path is operable in response to a first instruction, received by the circuitry for receiving an instruction, to accumulate (621 or 622) a first number of de-spread chips in the set of de-spread chips for producing at least one corresponding symbol.