Patents by Inventor Eric Chih-Fang Liu

Eric Chih-Fang Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10453686
    Abstract: Methods and systems for in-situ spacer reshaping for self-aligned multi-patterning are described. In an embodiment, a method of forming a spacer pattern on a substrate may include providing a substrate with a spacer. The method may also include performing a passivation treatment to form a passivation layer on the spacer. Additionally, the method may include performing spacer reshaping treatment to reshape the spacer. The method may also include controlling the passivation treatment and spacer reshaping treatment in order to achieve spacer formation objectives.
    Type: Grant
    Filed: April 13, 2017
    Date of Patent: October 22, 2019
    Assignee: Tokyo Electron Limited
    Inventors: Eric Chih-Fang Liu, Angelique Raley, Akiteru Ko
  • Publication number: 20190244826
    Abstract: Methods and systems for line cut by multi-color patterning techniques are presented. In an embodiment, a method may include providing a substrate. The method may also include forming a first feature on the substrate, the first feature having a cap formed of a first material. Additionally, the method may include forming a second feature on the substrate, the second feature having a cap formed of a second material. In still a further embodiment, the method may include selectively removing the second feature using an etch process that etches the first material at a first etch rate and etches the second material at a second etch rate, wherein the second etch rate is higher than the first etch rate.
    Type: Application
    Filed: February 6, 2019
    Publication date: August 8, 2019
    Inventors: Eric Chih-Fang Liu, Akiteru Ko
  • Publication number: 20190189445
    Abstract: Embodiments are disclosed for processing microelectronic workpieces to apply stress engineering to self-aligned multi-patterning (SAMP) processes. The disclosed processing methods utilize stress in a substrate in a SAMP process to improve resulting pattern parameters. Initially, a high stress film is deposited on the frontside and the backside of the substrate, and the high stress film provides biaxial stress to the substrate due to the deposition process for the high stress film. Next, a SAMP process is performed to form spacers in a spacer pattern. This spacer pattern is then transferred to underlying layers to form a patterned structure. The high stress film provides axial stress in at least one direction along a portion of the patterned structure during the pattern transfer thereby improving resulting pattern formation.
    Type: Application
    Filed: December 6, 2018
    Publication date: June 20, 2019
    Inventors: Eric Chih-Fang Liu, Akiteru Ko, David L. O'Meara
  • Publication number: 20190181041
    Abstract: A method for the via etching steps of a substrate manufacturing process flow is provided. The substrate processing techniques described provide for etching vias by providing a protection layer on the via sidewall during at least portions of the via etching process. In one embodiment, an atomic layer deposition (ALD) layer is formed on the via sidewalls to protect the dielectric layers through which the via is formed. The ALD layer may lessen bowing effects in low k dielectric layers which may result from etching barrier low k (blok) layers or from other process steps. After via formation, the ALD layer may be removed. The techniques are particularly suited for forming skip vias and other high aspect ratio vias formed in low k and ultra-low k dielectric layers.
    Type: Application
    Filed: December 7, 2018
    Publication date: June 13, 2019
    Inventors: Yen-Tien Lu, Xinghua Sun, Eric Chih-Fang Liu, Andrew W. Metz
  • Publication number: 20190103363
    Abstract: A method is provided for void-free Ru metal filling of features in a substrate. The method includes providing a substrate containing features, depositing a Ru metal layer in the features, removing the Ru metal layer from a field area around an opening of the features, and depositing additional Ru metal in the features, where the additional Ru metal is deposited in the features at a higher rate than on the field area. According to one embodiment, the additional Ru metal is deposited until the features are fully filled with Ru metal.
    Type: Application
    Filed: October 1, 2018
    Publication date: April 4, 2019
    Inventors: Kai-Hung Yu, Nicholas Joy, Eric Chih Fang Liu, David L. O'Meara, David Rosenthal, Masanobu Igeta, Cory Wajda, Gerrit J. Leusink
  • Patent number: 10170329
    Abstract: Embodiments of systems and methods for spacer formation for SAMP techniques are described. In an embodiment a method includes providing a substrate with a spacer having a conformal coating. The method may also include performing a spacer freeze treatment process. Additionally, the method may include performing an etch and clean process on the substrate. Further, the method may include controlling the spacer treatment process and etch and clean process in order to achieve spacer formation objectives.
    Type: Grant
    Filed: September 19, 2017
    Date of Patent: January 1, 2019
    Assignee: Tokyo Electron Limited
    Inventors: Eric Chih-Fang Liu, Akiteru Ko
  • Publication number: 20180239244
    Abstract: An additional non-photoresist layer may be formed on patterned photoresist layers. The additional layer may be preferentially formed on the tops of the photoresist layer versus the sidewalls of the photoresist layer. In addition, the additional layer may be preferential formed on the tops of the photoresist layer versus exposed surfaces of layers underlying the photoresist layer. In this manner, the patterned structures formed by the photoresist layer are less likely to have line opens due to photoresist height variability or the relative thinness of the photoresist height used. Further, the formation of the additional layer may be through a cyclic deposition/trim process. The trim step of the cyclic process may also serve as a descum step that helps reduce line bridging and scumming. In one embodiment, the additional non-photoresist layer may be an organic polymer layer.
    Type: Application
    Filed: February 22, 2018
    Publication date: August 23, 2018
    Inventors: Angelique D. Raley, Eric Chih-Fang Liu, Nihar Mohanty
  • Patent number: 10049892
    Abstract: Techniques herein include methods of processing photoresist patterns and photoresist materials for successful use in multi-patterning operations. Techniques include combinations of targeted deposition, curing, and trimming to provide a post-processed resist that effectively enables multi-patterning using photoresist materials to function as mandrels. Photoresist patterns and mandrels are hardened, strengthened, and/or dimensionally adjusted to provide desired dimensions and/or mandrels enabling straight sidewall spacers. Polymer is deposited with tapered profile to compensate for compressive stresses of various conformal or subsequent films to result in a vertical profile despite any compression.
    Type: Grant
    Filed: May 3, 2016
    Date of Patent: August 14, 2018
    Assignee: Tokyo Electron Limited
    Inventors: Nihar Mohanty, Eric Chih-Fang Liu, Elliott Franke
  • Publication number: 20180082851
    Abstract: Embodiments of systems and methods for spacer formation for SAMP techniques are described. In an embodiment a method includes providing a substrate with a spacer having a conformal coating. The method may also include performing a spacer freeze treatment process. Additionally, the method may include performing an etch and clean process on the substrate. Further, the method may include controlling the spacer treatment process and etch and clean process in order to achieve spacer formation objectives.
    Type: Application
    Filed: September 19, 2017
    Publication date: March 22, 2018
    Inventors: Eric Chih-Fang Liu, Akiteru Ko
  • Publication number: 20180061640
    Abstract: Methods and systems for in-situ spacer reshaping for self-aligned multi-patterning are described. In an embodiment, a method of forming a spacer pattern on a substrate may include providing a substrate with a spacer. The method may also include performing a passivation treatment to form a passivation layer on the spacer. Additionally, the method may include performing spacer reshaping treatment to reshape the spacer. The method may also include controlling the passivation treatment and spacer reshaping treatment in order to achieve spacer formation objectives.
    Type: Application
    Filed: April 13, 2017
    Publication date: March 1, 2018
    Inventors: Eric Chih-Fang Liu, Angelique Raley, Akiteru Ko
  • Patent number: 9870954
    Abstract: A method includes forming a first gate stack and a second gate stack over a first portion and a second portion, respectively, of a semiconductor substrate, masking the first portion of the semiconductor substrate, and with the first portion of the semiconductor substrate being masked, implanting the second portion of the semiconductor substrate with an etch-tuning element. The first portion and the second portion of the semiconductor substrate are etched simultaneously to form a first opening and a second opening, respectively, in the semiconductor substrate. The method further includes epitaxially growing a first semiconductor region in the first opening, and epitaxially growing a second semiconductor region in the second opening.
    Type: Grant
    Filed: February 2, 2016
    Date of Patent: January 16, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Eric Chih-Fang Liu, Srisuda Thitinun, Dai-Lin Wu, Ryan Chia-Jen Chen, Chao-Cheng Chen
  • Patent number: 9704974
    Abstract: A process of manufacturing a Fin-FET device, and the process includes following steps. An active fin structure and a dummy fin structure are formed from a substrate, and an isolation layer is covered over the active fin structure and the dummy fin structure. Then, the isolation layer above the dummy fin structure is removed, and the dummy fin structure is selectively etched, which a selective ratio of the dummy fin structure to the isolation layer is over 8.
    Type: Grant
    Filed: April 16, 2015
    Date of Patent: July 11, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chia-Wei Chang, An-Shen Chang, Eric Chih-Fang Liu, Ryan Chia-Jen Chen, Chia-Tai Lin, Chih-Tang Peng
  • Publication number: 20160329207
    Abstract: Techniques herein include methods of processing photoresist patterns and photoresist materials for successful use in multi-patterning operations. Techniques include combinations of targeted deposition, curing, and trimming to provide a post-processed resist that effectively enables multi-patterning using photoresist materials to function as mandrels. Photoresist patterns and mandrels are hardened, strengthened, and/or dimensionally adjusted to provide desired dimensions and/or mandrels enabling straight sidewall spacers. Polymer is deposited with tapered profile to compensate for compressive stresses of various conformal or subsequent films to result in a vertical profile despite any compression.
    Type: Application
    Filed: May 3, 2016
    Publication date: November 10, 2016
    Inventors: Nihar Mohanty, Eric Chih-Fang Liu, Elliott Franke
  • Publication number: 20160308027
    Abstract: A process of manufacturing a Fin-FET device, and the process includes following steps. An active fin structure and a dummy fin structure are formed from a substrate, and an isolation layer is covered over the active fin structure and the dummy fin structure. Then, the isolation layer above the dummy fin structure is removed, and the dummy fin structure is selectively etched, which a selective ratio of the dummy fin structure to the isolation layer is over 8.
    Type: Application
    Filed: April 16, 2015
    Publication date: October 20, 2016
    Inventors: Chia-Wei CHANG, An-Shen CHANG, Eric Chih-Fang LIU, Ryan Chia-Jen CHEN, Chia-Tai LIN, Chih-Tang PENG
  • Patent number: 9379220
    Abstract: Embodiments of the present disclosure are a method of forming a semiconductor device and a method of forming a FinFET device. An embodiment is a method of forming a semiconductor device, the method including forming a first dielectric layer over a substrate, forming a first hardmask layer on the first dielectric layer, and patterning the first hardmask layer to form a first hardmask portion with a first width. The method further includes forming a second dielectric layer on the first dielectric layer and the first hardmask portion, forming a third dielectric layer on the second dielectric layer, and etching the third dielectric layer and a portion of the second dielectric layer to form a first and second spacer on opposite sides of the first hardmask portion.
    Type: Grant
    Filed: November 10, 2014
    Date of Patent: June 28, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu Chao Lin, Cheng-Han Wu, Eric Chih-Fang Liu, Ryan Chia-Jen Chen, Chao-Cheng Chen
  • Publication number: 20160155672
    Abstract: A method includes forming a first gate stack and a second gate stack over a first portion and a second portion, respectively, of a semiconductor substrate, masking the first portion of the semiconductor substrate, and with the first portion of the semiconductor substrate being masked, implanting the second portion of the semiconductor substrate with an etch-tuning element. The first portion and the second portion of the semiconductor substrate are etched simultaneously to form a first opening and a second opening, respectively, in the semiconductor substrate. The method further includes epitaxially growing a first semiconductor region in the first opening, and epitaxially growing a second semiconductor region in the second opening.
    Type: Application
    Filed: February 2, 2016
    Publication date: June 2, 2016
    Inventors: Eric Chih-Fang Liu, Srisuda Thitinun, Dai-Lin Wu, Ryan Chia-Jen Chen, Chao-Cheng Chen
  • Patent number: 9263551
    Abstract: A method includes forming a first gate stack and a second gate stack over a first portion and a second portion, respectively, of a semiconductor substrate, masking the first portion of the semiconductor substrate, and with the first portion of the semiconductor substrate being masked, implanting the second portion of the semiconductor substrate with an etch-tuning element. The first portion and the second portion of the semiconductor substrate are etched simultaneously to form a first opening and a second opening, respectively, in the semiconductor substrate. The method further includes epitaxially growing a first semiconductor region in the first opening, and epitaxially growing a second semiconductor region in the second opening.
    Type: Grant
    Filed: October 11, 2013
    Date of Patent: February 16, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Eric Chih-Fang Liu, Srisuda Thitinun, Dai-Lin Wu, Ryan Chia-Jen Chen, Chao-Cheng Chen
  • Patent number: 9034706
    Abstract: A method includes etching a semiconductor substrate to form a recess in the semiconductor substrate, and reacting a surface layer of the semiconductor substrate to generate a reacted layer. The surface layer of the semiconductor substrate is in the recess. The reacted layer is then removed. An epitaxy is performed to grow a semiconductor material in the recess.
    Type: Grant
    Filed: April 19, 2013
    Date of Patent: May 19, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Eric Chih-Fang Liu, Tzu-Wei Kao, Ryan Chia-Jen Chen, Chao-Cheng Chen
  • Publication number: 20150132910
    Abstract: Embodiments of the present disclosure are a method of forming a semiconductor device and a method of forming a FinFET device. An embodiment is a method of forming a semiconductor device, the method including forming a first dielectric layer over a substrate, forming a first hardmask layer on the first dielectric layer, and patterning the first hardmask layer to form a first hardmask portion with a first width. The method further includes forming a second dielectric layer on the first dielectric layer and the first hardmask portion, forming a third dielectric layer on the second dielectric layer, and etching the third dielectric layer and a portion of the second dielectric layer to form a first and second spacer on opposite sides of the first hardmask portion.
    Type: Application
    Filed: November 10, 2014
    Publication date: May 14, 2015
    Inventors: Yu Chao Lin, Cheng-Han Wu, Eric Chih-Fang Liu, Ryan Chia-Jen Chen, Chao-Cheng Chen
  • Publication number: 20150104913
    Abstract: A method includes forming a first gate stack and a second gate stack over a first portion and a second portion, respectively, of a semiconductor substrate, masking the first portion of the semiconductor substrate, and with the first portion of the semiconductor substrate being masked, implanting the second portion of the semiconductor substrate with an etch-tuning element. The first portion and the second portion of the semiconductor substrate are etched simultaneously to form a first opening and a second opening, respectively, in the semiconductor substrate. The method further includes epitaxially growing a first semiconductor region in the first opening, and epitaxially growing a second semiconductor region in the second opening.
    Type: Application
    Filed: October 11, 2013
    Publication date: April 16, 2015
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Eric Chih-Fang Liu, Srisuda Thitinun, Dai-Lin Wu, Ryan Chia-Jen Chen, Chao-Cheng Chen