Abstract: A template wafer fabrication process is disclosed for high density indium bumping of microchips by using an innovative template wafer upon which the bumps are initially fabricated. Once fabricated, these bumps are transferred to the microchip, after which can be hybridized to another microchip. Such a template wafer is reusable, and thus provides an economical way to fabricate indium bumps. Reusability also eliminates nonuniformities in bump shape and size in serial processing of separate microchips, which is not the case for other indium bump fabrication processes. Such a fabrication process provides a way to form relatively tall indium bumps and accomplishes this without the standard thick photoresist liftoff process. The described process can be suitable for bump pitches under 10 microns, and is only limited by the resolution of the photolithography equipment used.

Abstract: A process is disclosed for high density indium bumping of microchips by using an innovative template wafer upon which the bumps are initially fabricated. Once fabricated, these bumps are transferred to the microchip, after which can be hybridized to another microchip. Such a template wafer is reusable, and thus provides an economical way to fabricate indium bumps. Reusability also eliminates nonuniformities in bump shape and size in serial processing of separate microchips, which is not the case for other indium bump fabrication processes. Such a fabrication process provides a way to form relatively tall indium bumps and accomplishes this without the standard thick photoresist liftoff process. The described process can be suitable for bump pitches under 10 microns, and is only limited by the resolution of the photolithography equipment used.

Abstract: A process is disclosed for high density indium bumping of microchips by using an innovative template wafer upon which the bumps are initially fabricated. Once fabricated, these bumps are transferred to the microchip, after which can be hybridized to another microchip. Such a template wafer is reusable, and thus provides an economical way to fabricate indium bumps. Reusability also eliminates nonuniformities in bump shape and size in serial processing of separate microchips, which is not the case for other indium bump fabrication processes. Such a fabrication process provides a way to form relatively tall indium bumps and accomplishes this without the standard thick photoresist liftoff process. The described process can be suitable for bump pitches under 10 microns, and is only limited by the resolution of the photolithography equipment used.

Abstract: A process is disclosed for high density indium bumping of microchips by using an innovative template wafer upon which the bumps are initially fabricated. Once fabricated, these bumps are transferred to the microchip, after which can be hybridized to another microchip. Such a template wafer is reusable, and thus provides an economical way to fabricate indium bumps. Reusability also eliminates nonuniformities in bump shape and size in serial processing of separate microchips, which is not the case for other indium bump fabrication processes. Such a fabrication process provides a way to form relatively tall indium bumps and accomplishes this without the standard thick photoresist liftoff process. The described process can be suitable for bump pitches under 10 microns, and is only limited by the resolution of the photolithography equipment used.

Abstract: A process is disclosed for high density indium bumping of microchips by using an innovative template wafer upon which the bumps are initially fabricated. Once fabricated, these bumps are transferred to the microchip, after which can be hybridized to another microchip. Such a template wafer is reusable, and thus provides an economical way to fabricate indium bumps. Reusability also eliminates nonuniformities in bump shape and size in serial processing of separate microchips, which is not the case for other indium bump fabrication processes. Such a fabrication process provides a way to form relatively tall indium bumps and accomplishes this without the standard thick photoresist liftoff process. The described process can be suitable for bump pitches under 10 microns, and is only limited by the resolution of the photolithography equipment used.

Abstract: A wafer bonded composite structure is provided for matching a coefficient of thermal expansion of a first semiconductor chip to a coefficient of thermal expansion of a second semiconductor chip in order to provide a thermally matched hybridized semiconductor chip assembly. The wafer bonded composite structure includes a first semiconductor chip having a top and a bottom surface. The first semiconductor chip has a coefficient of thermal expansion which is less than the coefficient of thermal expansion of the second semiconductor chip. Preferably, the first semiconductor chip is an readout integrated circuit (ROIC) and the second semiconductor chip is an infrared detector chip. Further, the wafer bonded composite structure also includes a substrate wafer bonded to a bottom surface of the first semiconductor chip to form the wafer bonded composite structure itself.

Abstract: The invention consists of a wafer-level expansion-matched design which forces a substrate to expand and contract at the same rate as a surface-mounted component, which reduces mechanical stress on the component. An embodiment of an expansion-matched MUX design consists of two pieces of silicon sandwiching a shim, which has a higher CTE than the silicon. By modifying the silicon thickness, shim thickness, and shim material, the CTE of the composite structure may be tailored. The composite structure is produced by a wafer level bonding approach to the balanced stack. Performing the bonding at the wafer level reduces die level touch time and improves planarity. Furthermore, a wafer level solution facilitates fabrication processes at elevated temperatures as the match occurs for both heating and cooling.

Abstract: A Group II-VI IR photodiode 10 has a passivation layer 16 overlying at least exposed surfaces of the p-n diode junction 15, the passivation layer being a compositionally graded layer comprised of Group II atoms diffused into a surface of the p-n diode junction. The passivation layer has a wider energy bandgap than the underlying diode material thereby repelling both holes and electrons away from the surface of the diode and resulting in improved diode operating characteristics. A cation substitution method of the invention includes the steps of preparing a surface to be passivated, such as by depleting an upper surface region of Group II atoms; depositing a layer comprised of a Group II material over the depleted surface region; and annealing the deposited layer and underlying Group II-VI material such that atoms of the deposited Group II layer diffuse into the underlying depleted surface region and fill cation vacancy sites within the depleted surface region.

Abstract: A photoresponsive device (10) includes a body comprised of semiconductor material comprised of elements selected from Group IIB-VIA; and at least one electrically conductive contact pad (20) formed over a surface of the semiconductor material. The at least one electrically conductive contact pad is comprised of metal nitride, such as MoN, and serves as a diffusion barrier between an Indium bump (22a, 22b) and the underlying semiconductor material. A passivation layer (18), such as a layer of wider bandgap CdTe, can be formed to overlie the surface of said semiconductor material. A p-n junction is contained within a mesa structure (10a) that comprises a portion of an n-type base layer (14) and a p-type cap layer (16). A first contact pad is disposed over the cap layer and a second contact pad is disposed over the base layer.

Abstract: A photoresponsive device wherein the device includes semiconductor material, such as a cap region (14a), comprised of elements selected from Group IIB-VIA. A molybdenum contact pad (16) is formed upon a surface of the cap region, and a molybdenum ground contact pad is formed on a surface of a base region (12). A wide bandgap semiconductor passivation layer (20) overlies the surface of the cap region and also partially overlies the molybdenum contact pad. A dielectric layer (22) overlies the passivation layer, and an indium bump (24) is formed upon the molybdenum contact pad. The dielectric layer is in intimate contact with side surfaces of the indium bump such that no portion of the molybdenum contact pad can be physically contacted from a top surface of the dielectric layer. This method eliminates the possibility of unwanted chemical reactions occurring between the In and the underlying contact pad metal.

Abstract: A photoresponsive device and a method of fabricating same, wherein the device includes semiconductor material, such as a cap region (14a), comprised of elements selected from Group IIB-VIA. A molybdenum contact pad (16) is formed upon a surface of the cap region, and a molybdenum ground contact pad is formed on a surface of a base region (12). A wide bandgap semiconductor passivation layer (20) overlies the surface of cap region and also partially overlies the molybdenum contact pad. A dielectric layer (22) overlies the passivation layer, and an indium bump (24) is formed upon the molybdenum contact pad. The indium bump extends upwardly from the molybdenum contact pad and through the dielectric layer. The dielectric layer is in intimate contact with side surfaces of the indium bump such that no portion of the molybdenum contact pad can be physically contacted from a top surface of the dielectric layer.

Abstract: A radiation detector 10 includes a first heterojunction 14A and a second heterojunction 16A electrically coupled together in series between a first electrical contact 18 and a second electrical contact 20. The detector comprises at least a three regions or layers including a first layer 12 having a first type of electrical conductivity, a second layer 14 having a second type of electrical conductivity, and a third layer 16 having the first type of electrical conductivity. The first and second heterojunctions are coupled in series and function electrically as two back-to-back diodes. During use the detector is coupled to a switchable bias source 22 that includes a source of positive bias (+Vb) 22A and a source of negative bias (-Vb) 22B. With +Vb applied across the detector the first heterojunction is in far forward bias and functions as a low resistance conductor, thereby contributing no significant amount of photocurrent to the circuit.

Abstract: A method and apparatus for detecting infrared radiation is disclosed. The apparatus comprises a substrate (12) having readout and signal processing circuits (14) integrated therein. The substrate (12) is formed from a material selected from the group consisting of silicon, gallium arsenide, or germanium. A first semiconductor layer (28) is grown on the substrate (12) from a material selected from the group consisting of mercury-cadmium-telluride, mercury-zinc-telluride, mercury-cadmium-selenide, mercury-zinc-selenide, mercury-cadmium-sulfide, mercury-zinc-sulfide, lead-tin-telluride, lead-tin-selenide, lead-tin-sulfide, indium-arsenide-antimonide, gallium-indium-antimonide, or gallium-antimonide-arsenide. A second semiconductor layer (30) is then grown on the first semiconductor layer (28).

Abstract: An array of photodiodes is comprised of a Group II-VI material, such as HgCdTe, which is processed to form a plurality of diode junctions. The array is fabricated by a method which comprises a first step of providing a radiation absorbing base 12 of p-type Hg.sub.(1-x) Cd.sub.x Te material. Each of the photodiodes is fabricated by depositing a layer 18 of wider bandgap passivation material over the substrate, depositing a photomask layer 26 over the passivation layer and selectively removing the passivation layer through openings within the photomask layer. One method of removing the passivation layer 18 is by ion milling which also converts the underlying p-type substrate material to n-type material. The lattice damage caused by the ion milling extends laterally outward such that the n-type region 14, and associated p-n diode junction 16, is disposed beneath the passivation layer 18.

Abstract: A method is disclosed for joining two semiconductor devices 10 and 10', each having a plurality of metallic contact bumps 12 and 12' on the major surfaces 14 and 14' thereof. The devices are etched to remove oxide 18 from the contact bumps and to prevent subsequent oxidation thereon. The devices are then oriented so that the bumps 12 and 12' on the respective devices are aligned opposite each other. By applying pressure to the devices, the bumps are caused to cold-weld together to form a single device 24.

Abstract: A detector assembly for reception of infrared radiation is formed as a composite structure of a detector array electrically connected by a set of contacts to a readout clip disposed on a backside of the assembly opposite a front side receiving incident radiation. Individual detectors are formed of layers of P-type and N-type semiconductor material, and are spaced apart from each other and from the readout chip by resilient electrically-insulating polymeric material which supports the detectors in their respective positions while allowing for thermally induced displacement of the detectors from their respective positions. A metallic grid on the front surface of the assembly provides a common electrical connection of the detectors to the readout chip. An antireflective coating may also be placed on the front surface of the assembly.

Abstract: A method for fabricating a metal insulator semiconductor includes first forming a substrate (10) having an array of switching elements formed therein. A plurality of deformable Indium pads (16) and (18) are then formed on the surface of the substrate and in contact with each of the switching elements. A superstrate is formed from a layer of mercury cadmium telluride (32) and a layer of dielectric insulating material (34). The superstrate is pressed down adjacent the substrate (10) with the upper surface of the conductive gates (16) and (18) contracting the lower surface of the dielectric layer (34). The deformable pads (16) and (18) conform to the lower surface of the dielectric layer (34). Epoxy (36) is then disposed in the interstices of the device to provide an adhesive force between the substrate (10) and the superstrate.

Abstract: A method for fabricating a metal insulator semiconductor includes first forming a substrate (10) having an array of switching elements formed therein. A plurality of deformable Indium pads (16) and (18) are then formed on the surface of the substrate and in contact with each of the switching elements. A superstrate is formed from a layer of mercury cadmium telluride (32) and a layer of dielectric insulating material (34). The superstrate is pressed down adjacent the substrate (10) with the upper surface of the conductive gates (16) and (18) contacting the lower surface of the dielectric layer (34). The deformable pads (16) and (18) conform to the lower surface of the dielectric layer (34). Epoxy (36) is then disposed in the interstices of the device to provide an adhesive force between the substrate (10) and the superstrate.

Abstract: Laser patterning of metallization is done by transmitting laser energy through a liquid film directly in contact with the metallization to be patterned. When the metal is evaporated by the laser energy, the vapor is condensed immediately by the liquid film. This prevents redeposition of metal on the patterned surface and suspends the removed metal in the liquid so that it may be reclaimed by filtration.

Abstract: A method for patterning layers of material on a substrate without photoresist by using a selective sublimation process. Differences in thermal conductivity of materials underneath a layer of material to be patterned cause patterning by sublimation over areas of low thermal conductivity, initiated by a pulsed or swept radiated energy source.