Patents by Inventor Eric G. Liskay
Eric G. Liskay has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240129503Abstract: Described herein is a data processing system having a multisample antialiasing compressor coupled to a texture unit and shader execution array. In one embodiment, the data processing system includes a memory device to store a multisample render target, the multisample render target to store color data for a set of sample locations of each pixel in a set of pixels; and general-purpose graphics processor comprising a multisample antialiasing compressor to apply multisample antialiasing compression to color data generated for the set of sample locations of a first pixel in the set of pixels and a multisample render cache to store color data generated for the set of sample locations of the first pixel in the set of pixels, wherein color data evicted from the multisample render cache is to be stored to the multisample render target.Type: ApplicationFiled: October 23, 2023Publication date: April 18, 2024Applicant: Intel CorporationInventors: Prasoonkumar Surti, Abhishek R. Appu, Michael J. Norris, Eric G. Liskay
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Patent number: 11856213Abstract: Described herein is a data processing system having a multisample antialiasing compressor coupled to a texture unit and shader execution array. In one embodiment, the data processing system includes a memory device to store a multisample render target, the multisample render target to store color data for a set of sample locations of each pixel in a set of pixels; and general-purpose graphics processor comprising a multisample antialiasing compressor to apply multisample antialiasing compression to color data generated for the set of sample locations of a first pixel in the set of pixels and a multisample render cache to store color data generated for the set of sample locations of the first pixel in the set of pixels, wherein color data evicted from the multisample render cache is to be stored to the multisample render target.Type: GrantFiled: July 12, 2022Date of Patent: December 26, 2023Assignee: Intel CorporationInventors: Prasoonkumar Surti, Abhishek R. Appu, Michael J. Norris, Eric G. Liskay
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Patent number: 11574382Abstract: Examples described herein relate to a decompression engine that can request compressed data to be transferred over a memory bus. In some cases, the memory bus is a width that requires multiple data transfers to transfer the requested data. In a case that requested data is to be presented in-order to the decompression engine, a re-order buffer can be used to store entries of data. When a head-of-line entry is received, the entry can be provided to the decompression engine. When a last entry in a group of one or more entries is received, all entries in the group are presented in-order to the decompression engine. In some examples, a decompression engine can borrow memory resources allocated for use by another memory client to expand a size of re-order buffer available for use. For example, a memory client with excess capacity and a slowest growth rate can be chosen to borrow memory resources from.Type: GrantFiled: September 3, 2021Date of Patent: February 7, 2023Assignee: Intel CorporationInventors: Abhishek R. Appu, Eric G. Liskay, Prasoonkumar Surti, Sudhakar Kamma, Karthik Vaidyanathan, Rajasekhar Pantangi, Altug Koker, Abhishek Rhisheekesan, Shashank Lakshminarayana, Priyanka Ladda, Karol A. Szerszen
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Publication number: 20230005186Abstract: A mechanism is described for facilitating smart compression/decompression schemes at computing devices. A method of embodiments, as described herein, includes unifying a first compression scheme relating to three-dimensional (3D) content and a second compression scheme relating to media content into a unified compression scheme to perform compression of one or more of the 3D content and the media content relating to a processor including a graphics processor.Type: ApplicationFiled: June 21, 2022Publication date: January 5, 2023Applicant: Intel CorporationInventors: Abhishek R. Appu, Kiran C. Veernapu, Prasoonkumar Surti, Joydeep Ray, Altug Koker, Eric G. Liskay
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Publication number: 20230007285Abstract: Described herein is a data processing system having a multisample antialiasing compressor coupled to a texture unit and shader execution array. In one embodiment, the data processing system includes a memory device to store a multisample render target, the multisample render target to store color data for a set of sample locations of each pixel in a set of pixels; and general-purpose graphics processor comprising a multisample antialiasing compressor to apply multisample antialiasing compression to color data generated for the set of sample locations of a first pixel in the set of pixels and a multisample render cache to store color data generated for the set of sample locations of the first pixel in the set of pixels, wherein color data evicted from the multisample render cache is to be stored to the multisample render target.Type: ApplicationFiled: July 12, 2022Publication date: January 5, 2023Applicant: Intel CorporationInventors: Prasoonkumar Surti, Abhishek R. Appu, Michael J. Norris, Eric G. Liskay
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Patent number: 11399194Abstract: Described herein is an apparatus having color compression circuitry coupled to a texture unit and shader execution array. The color compression circuitry performs lossless delta color compression of pixel color data provided by the shader execution array and texture unit to generate compressed color data. The compressed color data is stored at one or more levels of a multilevel cache subsystem.Type: GrantFiled: April 12, 2021Date of Patent: July 26, 2022Assignee: Intel CorporationInventors: Prasoonkumar Surti, Abhishek R. Appu, Michael J. Norris, Eric G. Liskay
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Patent number: 11393131Abstract: A mechanism is described for facilitating smart compression/decompression schemes at computing devices. A method of embodiments, as described herein, includes unifying a first compression scheme relating to three-dimensional (3D) content and a second compression scheme relating to media content into a unified compression scheme to perform compression of one or more of the 3D content and the media content relating to a processor including a graphics processor.Type: GrantFiled: September 3, 2020Date of Patent: July 19, 2022Assignee: Intel CorporationInventors: Abhishek R. Appu, Kiran C. Veernapu, Prasoonkumar Surti, Joydeep Ray, Altug Koker, Eric G. Liskay
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Publication number: 20220058765Abstract: Examples described herein relate to a decompression engine that can request compressed data to be transferred over a memory bus. In some cases, the memory bus is a width that requires multiple data transfers to transfer the requested data. In a case that requested data is to be presented in-order to the decompression engine, a re-order buffer can be used to store entries of data. When a head-of-line entry is received, the entry can be provided to the decompression engine. When a last entry in a group of one or more entries is received, all entries in the group are presented in-order to the decompression engine. In some examples, a decompression engine can borrow memory resources allocated for use by another memory client to expand a size of re-order buffer available for use. For example, a memory client with excess capacity and a slowest growth rate can be chosen to borrow memory resources from.Type: ApplicationFiled: September 3, 2021Publication date: February 24, 2022Inventors: Abhishek R. APPU, Eric G. LISKAY, Prasoonkumar SURTI, Sudhakar KAMMA, Karthik VAIDYANATHAN, Rajasekhar PANTANGI, Altug KOKER, Abhishek RHISHEEKESAN, Shashank LAKSHMINARAYANA, Priyanka LADDA, Karol A. SZERSZEN
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Patent number: 11113783Abstract: Examples described herein relate to a decompression engine that can request compressed data to be transferred over a memory bus. In some cases, the memory bus is a width that requires multiple data transfers to transfer the requested data. In a case that requested data is to be presented in-order to the decompression engine, a re-order buffer can be used to store entries of data. When a head-of-line entry is received, the entry can be provided to the decompression engine. When a last entry in a group of one or more entries is received, all entries in the group are presented in-order to the decompression engine. In some examples, a decompression engine can borrow memory resources allocated for use by another memory client to expand a size of re-order buffer available for use. For example, a memory client with excess capacity and a slowest growth rate can be chosen to borrow memory resources from.Type: GrantFiled: November 13, 2019Date of Patent: September 7, 2021Assignee: Intel CorporationInventors: Abhishek R. Appu, Eric G. Liskay, Prasoonkumar Surti, Sudhakar Kamma, Karthik Vaidyanathan, Rajasekhar Pantangi, Altug Koker, Abhishek Rhisheekesan, Shashank Lakshminarayana, Priyanka Ladda, Karol A. Szerszen
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Publication number: 20210258592Abstract: Described herein is an apparatus having color compression circuitry coupled to a texture unit and shader execution array. The color compression circuitry performs lossless delta color compression of pixel color data provided by the shader execution array and texture unit to generate compressed color data.Type: ApplicationFiled: April 12, 2021Publication date: August 19, 2021Applicant: Intel CorporationInventors: Prasoonkumar Surti, Abhishek R. Appu, Michael J. Norris, Eric G. Liskay
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Publication number: 20210142438Abstract: Examples described herein relate to a decompression engine that can request compressed data to be transferred over a memory bus. In some cases, the memory bus is a width that requires multiple data transfers to transfer the requested data. In a case that requested data is to be presented in-order to the decompression engine, a re-order buffer can be used to store entries of data. When a head-of-line entry is received, the entry can be provided to the decompression engine. When a last entry in a group of one or more entries is received, all entries in the group are presented in-order to the decompression engine. In some examples, a decompression engine can borrow memory resources allocated for use by another memory client to expand a size of re-order buffer available for use. For example, a memory client with excess capacity and a slowest growth rate can be chosen to borrow memory resources from.Type: ApplicationFiled: November 13, 2019Publication date: May 13, 2021Inventors: Abhishek R. APPU, Eric G. LISKAY, Prasoonkumar SURTI, Sudhakar KAMMA, Karthik VAIDYANATHAN, Rajasekhar PANTANGI, Altug KOKER, Abhishek RHISHEEKESAN, Shashank LAKSHMINARAYANA, Priyanka LADDA, Karol A. Szerszen
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Patent number: 11006138Abstract: Described herein is a data processing system comprising a memory device to store a multisample render target and a general-purpose graphics processor comprising a multisample antialiasing compressor and a multisample render cache. The multisample render target can store color data for a set of sample locations of each pixel in a set of pixels. The multisample antialiasing compressor can apply multisample antialiasing compression to color data generated for the set of sample locations of a first pixel in the set of pixels. The multisample render cache can store color data generated for the set of sample locations of the first pixel in the set of pixels. Color data evicted from the multisample render cache is stored to the multisample render target.Type: GrantFiled: October 23, 2019Date of Patent: May 11, 2021Assignee: Intel CorporationInventors: Prasoonkumar Surti, Abhishek R. Appu, Michael J. Norris, Eric G. Liskay
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Publication number: 20210125378Abstract: A mechanism is described for facilitating smart compression/decompression schemes at computing devices. A method of embodiments, as described herein, includes unifying a first compression scheme relating to three-dimensional (3D) content and a second compression scheme relating to media content into a unified compression scheme to perform compression of one or more of the 3D content and the media content relating to a processor including a graphics processor.Type: ApplicationFiled: September 3, 2020Publication date: April 29, 2021Applicant: Intel CorporationInventors: ABHISHEK R. APPU, Kiran C. Veernapu, Prasoonkumar Surti, Joydeep Ray, Altug Koker, Eric G. Liskay
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Patent number: 10769818Abstract: A mechanism is described for facilitating smart compression/decompression schemes at computing devices. A method of embodiments, as described herein, includes unifying a first compression scheme relating to three-dimensional (3D) content and a second compression scheme relating to media content into a unified compression scheme to perform compression of one or more of the 3D content and the media content relating to a processor including a graphics processor.Type: GrantFiled: April 9, 2017Date of Patent: September 8, 2020Assignee: INTEL CORPORATIONInventors: Abhishek R. Appu, Kiran C. Veernapu, Prasoonkumar Surti, Joydeep Ray, Altug Koker, Eric G. Liskay
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Publication number: 20200068211Abstract: Described herein is a data processing system comprising a memory device to store a multisample render target and a general-purpose graphics processor comprising a multisample antialiasing compressor and a multisample render cache. The multisample render target can store color data for a set of sample locations of each pixel in a set of pixels. The multisample antialiasing compressor can apply multisample antialiasing compression to color data generated for the set of sample locations of a first pixel in the set of pixels. The multisample render cache can store color data generated for the set of sample locations of the first pixel in the set of pixels. Color data evicted from the multisample render cache is stored to the multisample render target.Type: ApplicationFiled: October 23, 2019Publication date: February 27, 2020Applicant: Intel CorporationInventors: Prasoonkumar Surti, Abhishek R. Appu, Michael J. Norris, Eric G. Liskay
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Patent number: 10499073Abstract: One embodiment provides for a general-purpose graphics processor comprising a multisample antialiasing compression module to perform planar multi-sample anti-aliasing, the multisample antialiasing compression module to analyze color data for a set of sample locations of a first pixel; determine a first plane to allocate for the first pixel, wherein the first plane is a lowest order plane to be allocated for the first pixel; and merge a plane allocation for the first pixel with a plane allocation for a second pixel in response to a determination that the first plane is the lowest order plane to be allocated for the second pixel.Type: GrantFiled: December 20, 2018Date of Patent: December 3, 2019Assignee: Intel CorporationInventors: Prasoonkumar Surti, Abhishek R. Appu, Michael J. Norris, Eric G. Liskay
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Patent number: 10438569Abstract: A mechanism is described for facilitating consolidated compression/de-compression of graphics data streams of varying types at computing devices. A method of embodiments, as described herein, includes generating a common sector cache relating to a graphics processor. The method may further include performing a consolidated compression of multiple types of graphics data streams associated with the graphics processor using the common sector cache.Type: GrantFiled: April 17, 2017Date of Patent: October 8, 2019Assignee: INTEL CORPORATIONInventors: Abhishek R. Appu, Joydeep Ray, Prasoonkumar Surti, Altug Koker, Kiran C. Veernapu, Eric G. Liskay
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Publication number: 20190132603Abstract: One embodiment provides for a general-purpose graphics processor comprising a multisample antialiasing compression module to perform planar multi-sample anti-aliasing, the multisample antialiasing compression module to analyze color data for a set of sample locations of a first pixel; determine a first plane to allocate for the first pixel, wherein the first plane is a lowest order plane to be allocated for the first pixel; and merge a plane allocation for the first pixel with a plane allocation for a second pixel in response to a determination that the first plane is the lowest order plane to be allocated for the second pixel.Type: ApplicationFiled: December 20, 2018Publication date: May 2, 2019Applicant: Intel CorporationInventors: Prasoonkumar Surti, Abhishek R. Appu, Michael J. Norris, Eric G. Liskay
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Patent number: 10212443Abstract: One embodiment provides for a general-purpose graphics processor comprising a multisample antialiasing compression module to perform planar multi-sample anti-aliasing, the multisample antialiasing compression module to analyze color data for a set of sample locations of a first pixel; determine a first plane to allocate for the first pixel, wherein the first plane is a lowest order plane to be allocated for the first pixel; and merge a plane allocation for the first pixel with a plane allocation for a second pixel in response to a determination that the first plane is the lowest order plane to be allocated for the second pixel.Type: GrantFiled: January 17, 2018Date of Patent: February 19, 2019Assignee: Intel CorporationInventors: Prasoonkumar Surti, Abhishek R. Appu, Michael J. Norris, Eric G. Liskay
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Publication number: 20180308450Abstract: Methods and apparatus relating to techniques for provision of color mapping for better compression ratio are described. In an embodiment, a plurality of bits are moved from all channels of a first Red Green Blue Alpha (RGBA) space to an alpha channel of a second RGBA space. The plurality of the bits are selected from higher order bits of the first RGBA space. Other embodiments are also disclosed and claimed.Type: ApplicationFiled: April 21, 2017Publication date: October 25, 2018Applicant: Intel CorporationInventors: Abhishek R. Appu, Eric J. Hoekstra, Subramaniam Maiyuran, Prasoonkumar Surti, Eric G. Liskay, Joydeep Ray, Michael J. Norris, Wenyin Fu, Altug Koker