Abstract: Systems and methods are provided for reducing power in in-memory computing, matrix-vector computations, and neural networks. An apparatus for in-memory computing using charge-domain circuit operation includes transistors configured as memory bit cells, transistors configured to perform in-memory computing using the memory bit cells, capacitors configured to store a result of in-memory computing from the memory bit cells, and switches, wherein, based on a setting of each of the switches, the charges on at least a portion of the plurality of capacitors are shorted together. Shorting together the plurality of capacitors yields a computation result.

Abstract: A system for ultrasound beamforming is provided, including a sampled analog beamformer, an array of ultrasound transducers, and a high voltage amplifier coupled to the sampled analog beamformer and the array of ultrasound transducers. The sampled analog beamformer includes a sampled analog filter for filtering an incoming analog signal and adding a fractional delay, and transmitting a filtered analog ultrasound signal. The array of ultrasound transducers further transmits the filtered analog ultrasound signal. The high voltage amplifier drives transducers in the array of ultrasound transducers.

Abstract: Systems and methods are provided for reducing power in in-memory computing, matrix-vector computations, and neural networks. An apparatus for in-memory computing using charge-domain circuit operation includes transistors configured as memory bit cells, transistors configured to perform in-memory computing using the memory bit cells, capacitors configured to store a result of in-memory computing from the memory bit cells, and switches, wherein, based on a setting of each of the switches, the charges on at least a portion of the plurality of capacitors are shorted together. Shorting together the plurality of capacitors yields a computation result.

Abstract: Systems and methods of implementing a more efficient and less resource-intensive CNN are disclosed herein. In particular, applications of CNN in the analog domain using Sampled Analog Technology (SAT) methods are disclosed. Using a CNN design with SAT results in lower power usage and faster operation as compared to a CNN design with digital logic and memory. The lower power usage of a CNN design with SAT can allow for sensor devices that also detect features at very low power for isolated operation.

Abstract: Systems and methods are provided for reducing power in in-memory computing, matrix-vector computations, and neural networks. An apparatus for in-memory computing using charge-domain circuit operation includes transistors configured as memory bit cells, transistors configured to perform in-memory computing using the memory bit cells, capacitors configured to store a result of in-memory computing from the memory bit cells, and switches, wherein, based on a setting of each of the switches, the charges on at least a portion of the plurality of capacitors are shorted together. Shorting together the plurality of capacitors yields a computation result.

Abstract: A system for ultrasound beamforming is provided, including a sampled analog beamformer, an array of ultrasound transducers, and a high voltage amplifier coupled to the sampled analog beamformer and the array of ultrasound transducers. The sampled analog beamformer includes a sampled analog filter for filtering an incoming analog signal and adding a fractional delay, and transmitting a filtered analog ultrasound signal. The array of ultrasound transducers further transmits the filtered analog ultrasound signal. The high voltage amplifier drives transducers in the array of ultrasound transducers.

Abstract: A sampled analog beamformer for ultrasound beamforming includes an array of transducers for transmitting analog signals and receiving reflected analog signals, and a sampled analog filter for filtering the received reflected analog. The sampled analog filter includes a delay line for adding a delay to each of the received reflected analog signals. Using a sampled analog filter in an ultrasound beamforming system reduces the power usage of the system and decreases the number of components in the system.

Abstract: A system for ultrasound beamforming is provided, including a sampled analog beamformer, an array of ultrasound transducers, and a high voltage amplifier coupled to the sampled analog beamformer and the array of ultrasound transducers. The sampled analog beamformer includes a sampled analog filter for filtering an incoming analog signal and adding a fractional delay, and transmitting a filtered analog ultrasound signal. The array of ultrasound transducers further transmits the filtered analog ultrasound signal. The high voltage amplifier drives transducers in the array of ultrasound transducers.

Abstract: Systems and methods are provided for compressing and decompressing data in an ultrasound beamformer. The systems and methods include an encoder for compressing delay data based at least in part on a smoothness of a delay profile, and for compressing apodization data based at least in part on a smoothness of an apodization profile.

Abstract: Systems and methods for synchronous demodulation using passive sampled analog filtering are disclosed. A system for synchronous demodulation includes an input channel for accepting an input signal, a first passive sampled analog filter for filtering the input signal, a mixer for mixing the filtered input signal and outputting a mixed signal, a second passive sampled analog filter for filtering the mixed signal, and an output channel for outputting the filtered mixed signal.

Abstract: Systems and methods are disclosed for a noise-shaping successive approximation register (SAR) analog-to-digital-converter (ADC) using Sampled Analog Technology (SAT) filter techniques for filter construction. A SAR ADC includes an SAR for receiving an analog input signal and outputting a digital decision, a digital-to-analog converter and logic circuitry for converting the digital decision of the SAR to a present analog residue for a present conversion cycle, a filter for processing a previous analog residue from a previous conversion cycle, and for feeding a processed previous analog residue back to the SAR, a summer for summing the processed previous analog residue from the filter and the present analog residue, and generating a summer output, and a comparator for comparing the summer output and a first reference signal and generating a comparator output. The filter includes a capacitor array for filtering the previous analog residue to generate the processed previous analog residue.

Abstract: Systems and methods are provided for reducing power in in-memory computing, matrix-vector computations, and neural networks. An apparatus for in-memory computing using charge-domain circuit operation includes transistors configured as memory bit cells, transistors configured to perform in-memory computing using the memory bit cells, capacitors configured to store a result of in-memory computing from the memory bit cells, and switches, wherein, based on a setting of each of the switches, the charges on at least a portion of the plurality of capacitors are shorted together. Shorting together the plurality of capacitors yields a computation result.

Abstract: Systems and methods for synchronous demodulation using passive sampled analog filtering are disclosed. A system for synchronous demodulation includes an input channel for accepting an input signal, a first passive sampled analog filter for filtering the input signal, a mixer for mixing the filtered input signal and outputting a mixed signal, a second passive sampled analog filter for filtering the mixed signal, and an output channel for outputting the filtered mixed signal.

Abstract: A sampled analog circuit is divided into at least two segments, each segment receiving sampled analog data and a respective subset of bits of a filter coefficient. The at least two segments can have digital-to-capacitance circuits with substantially identical ranges of capacitance values. One or more outputs from the segments can be scaled to reflect a position of the subset of bits in the bits of the filter coefficient, and thereafter added in the analog domain to produce a filtered output signal that may then be digitized. Alternatively, the outputs from the segments may be digitized before being scaled and/or added in the digital domain.

Abstract: Systems and methods are disclosed for a noise-shaping successive approximation register (SAR) analog-to-digital-converter (ADC) using Sampled Analog Technology (SAT) filter techniques for filter construction. A SAR ADC includes an SAR for receiving an analog input signal and outputting a digital decision, a digital-to-analog converter and logic circuitry for converting the digital decision of the SAR to a present analog residue for a present conversion cycle, a filter for processing a previous analog residue from a previous conversion cycle, and for feeding a processed previous analog residue back to the SAR, a summer for summing the processed previous analog residue from the filter and the present analog residue, and generating a summer output, and a comparator for comparing the summer output and a first reference signal and generating a comparator output. The filter includes a capacitor array for filtering the previous analog residue to generate the processed previous analog residue.

Abstract: Systems and methods of implementing a more efficient and less resource-intensive CNN are disclosed herein. In particular, applications of CNN in the analog domain using Sampled Analog Technology (SAT) methods are disclosed. Using a CNN design with SAT results in lower power usage and faster operation as compared to a CNN design with digital logic and memory. The lower power usage of a CNN design with SAT can allow for sensor devices that also detect features at very low power for isolated operation.

Abstract: A sampled analog beamformer for ultrasound beamforming includes an array of transducers for transmitting analog signals and receiving reflected analog signals, and a sampled analog filter for filtering the received reflected analog. The sampled analog filter includes a delay line for adding a delay to each of the received reflected analog signals. Using a sampled analog filter in an ultrasound beamforming system reduces the power usage of the system and decreases the number of components in the system.

Abstract: Many processes for audio signal processing can benefit from voice activity detection, which aims to detect the presence of speech as opposed to silence or noise. The present disclosure describes, among other things, leveraging energy-based features of voice and insights on first and second formant frequencies of vowels to provide a low-complexity and low-power voice activity detector. A pair of two channels is provided whereby each channel is configured to detect voice activity in respective frequency bands of interest. Simultaneous activity detected in both channels can be a sufficient condition for determining that voice is present. More channels or pairs of channels can be used to detect different types of voices to improve detection and/or to detect voices present in different audio streams.

Abstract: A signal processing device has a first discrete time analog signal processing section, which has an input, an output, a plurality of charge storage elements, and plurality of switch elements coupling the charge storage elements. The device has a controller coupled to the first signal processing section configured to couple different subsets of the charge elements of the first signal processing section in successive operating phases to apply a signal processing function to an analog signal presented at the input of the first signal processing section and provide a result of the applying of the signal processing function as an analog signal to the output of first signal processing section. The signal processing function of the first signal processing section comprises a combination of a filtering function operating at a first sampling rate and one or more modulation functions operating at corresponding modulation rates lower than the first sampling rate.

Abstract: An integrated circuit implements at least part of a phase locked loop (PLL). The integrated circuit includes a sampled analog loop filter for the PLL. The loop filter includes a first input for receiving a signal representative of a phase difference between a reference clock signal and a first clock signal, a first output for providing a frequency control signal for controlling a frequency of an oscillator, a clock input for accepting a loop timing clock signal for controlling timing of operation of the loop filter, and a digital control input for configuring a response of the loop filter according to a plurality of control values. In some examples, the loop filter includes charge storage elements coupled by controllable switches, and control circuitry for transferring charge among the charge storage elements to yield the configured response of the loop filter.