Patents by Inventor Eric Kuo-Uei Yang

Eric Kuo-Uei Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20110314473
    Abstract: A distributed multi-processor out-of-order system includes multiple processors, an arbiter, a data dispatcher, a memory controller, a storage unit, multiple memory access requests issued by the multiple processors, and multiple data units that provide the results of the multiple memory access requests. Each of the multiple memory access requests includes a tag that identifies the priority of the processor that issued the memory access request, a processor identification number that identifies the processor that issued the request, and a processor access sequence number that identifies the order that the particular one of the processors issued the request. Each of the data units also includes a tag that specifics the processor identification number, the processor access sequence number, and a data sequence number that identifies the order of the data units satisfying the corresponding one of the memory requests.
    Type: Application
    Filed: August 29, 2011
    Publication date: December 22, 2011
    Applicant: BAY MICROSYSTEMS, INC.
    Inventors: Eric Kuo-Uei Yang, Jun-Wen Tsong
  • Patent number: 8010751
    Abstract: A distributed multi-processor out-of-order system includes multiple processors, an arbiter, a data dispatcher, a memory controller, a storage unit, multiple memory access requests issued by the multiple processors, and multiple data units that provide the results of the multiple memory access requests. Each of the multiple memory access requests includes a tag that identifies the priority of the processor that issued the memory access request, a processor identification number that identifies the processor that issued the request, and a processor access sequence number that identifies the order that the particular one of the processors issued the request. Each of the data units also includes a tag that specifies the processor identification number, the processor access sequence number, and a data sequence number that identifies the order of the data units satisfying the corresponding one of the memory requests.
    Type: Grant
    Filed: April 14, 2003
    Date of Patent: August 30, 2011
    Assignee: Bay Microsystems
    Inventors: Eric Kuo-Uei Yang, Jun-Wen Tsong
  • Publication number: 20030233503
    Abstract: A distributed multi-processor out-of-order system includes multiple processors, an arbiter, a data dispatcher, a memory controller, a storage unit, multiple memory access requests issued by the multiple processors, and multiple data units that provide the results of the multiple memory access requests. Each of the multiple memory access requests includes a tag that identifies the priority of the processor that issued the memory access request, a processor identification number that identifies the processor that issued the request, and a processor access sequence number that identifies the order that the particular one of the processors issued the request. Each of the data units also includes a tag that specifies the processor identification number, the processor access sequence number, and a data sequence number that identifies the order of the data units satisfying the corresponding one of the memory requests.
    Type: Application
    Filed: April 14, 2003
    Publication date: December 18, 2003
    Inventors: Eric Kuo-Uei Yang, Jun-Wen Tsong
  • Patent number: 6653955
    Abstract: An apparatus comprising a first circuit and a logic circuit. The first circuit may be configured to generate a first output signal in response to (i) an input signal, (ii) a first control signal and (iii) a second control signal. The logic circuit may be configured to generate (i) a second output signal, (ii) the first control signal and (iii) the second control signal in response to a predetermined portion of the input signal.
    Type: Grant
    Filed: May 9, 2002
    Date of Patent: November 25, 2003
    Assignee: LSI Logic Corporation
    Inventor: Eric Kuo-Uei Yang
  • Publication number: 20030210163
    Abstract: An apparatus comprising a first circuit and a logic circuit. The first circuit may be configured to generate a first output signal in response to (i) an input signal, (ii) a first control signal and (iii) a second control signal. The logic circuit may be configured to generate (i) a second output signal, (ii) the first control signal and (iii) the second control signal in response to a predetermined portion of the input signal.
    Type: Application
    Filed: May 9, 2002
    Publication date: November 13, 2003
    Applicant: LSI LOGIC CORPORATION
    Inventor: Eric Kuo-Uei Yang