Abstract: Power management techniques for a Universal Serial Bus (USB) include determining an idle period on one or more USB ports by a main controller circuit of a USB host controller. The main controller circuit signals a suspend to a Power Management Controller (PMC) sub-circuit of the USB host controller, in response to the determined idle period. The PMC sub-circuit stores one or more operating parameters of the one or more USB ports in response to the suspend signal. The PMC sub-circuit also maintains the idle state on the one or more USB ports in response to the suspend signal. Thereafter, the main controller circuit is placed in a low energy state while the PMC sub-circuit maintains the idle state.

Abstract: Power management techniques for a Universal Serial Bus (USB) include determining an idle period on one or more USB ports by a main controller circuit of a USB host controller. The main controller circuit signals a suspend to a Power Management Controller (PMC) sub-circuit of the USB host controller, in response to the determined idle period. The PMC sub-circuit stores one or more operating parameters of the one or more USB ports in response to the suspend signal. The PMC sub-circuit also maintains the idle state on the one or more USB ports in response to the suspend signal. Thereafter, the main controller circuit is placed in a low energy state while the PMC sub-circuit maintains the idle state.

Abstract: A system and method for performing dynamic trimming. Specifically, the system comprises a clock for generating a reference clock signal. The reference clock signal comprises a first frequency that is a factor of a second frequency of a signal (e.g., data clock signal from DDR memory). A counter is coupled to the clock and generates a plurality of clock pulses based on pulses of the reference clock signal. The plurality of clock pulses is generated at a slower frequency from the first frequency for low power operation. A phase length detector is coupled to the counter and comprises a trimmer chain for detecting an average length of at least one of the generated plurality of clock pulses. A transformation module is coupled to the phase length detector for transforming the average length to a phase delay of the signal.