Abstract: A method and apparatus for distributed on-chip debug triggering is presented. A first bus includes a plurality of lines and a debugging state machine configurable to monitor the plurality of lines of the first bus. One or more nodes are configurable to detect triggering events and provide, in response to detecting one or more triggering events, signals to the debugging state machine using a first subset of the plurality of lines that is allocated to the node(s).

Abstract: The present invention provides a method and apparatus for dynamically configuring debug triggering patterns. One example embodiment of the method includes comparing values of bits received on a first subset of a plurality of lines of a bus with a first pattern of bits and capturing values of bits received on a second subset of the plurality of lines of the bus in response to the comparison indicating that the values of the bits received on the first subset of the lines match the first pattern of bits. The exemplary embodiment of the method also includes defining a second pattern for triggering a debug action using the captured values.

Abstract: Embodiments include methods for performing various operations in a computing system that includes an electronic module and a debug circuit. The method includes programming the debug circuit to monitor for pre-selected triggers produced by the computing system, and to perform actions in response to detecting the pre-select triggers. For example, in response to various pre-selected triggers, the debug circuit may, among other things: perform state transitions and log information indicating whether or not the state transitions were performed; monitor various signals when the debug circuit has determined that a test escape has occurred; and/or perform one or more actions that initiate stopping one or more clocks in response to certain pre-selected triggers.

Abstract: An integrated circuit with debug capability includes a first packer and synchronizer to combine a multiple number of values of a first trigger signal received from a first circuit to form a first packed trigger signal and to output a synchronized first packed trigger signal in response to a trigger clock signal, the first trigger signal being synchronous with a first source clock signal, a first logic gate to provide a first output trigger signal indicative of whether any of the first multiple number of values of the first trigger signal in the first synchronized packed trigger signal is in a first state, and a debug state machine responsive to the first output trigger signal to selectively provide a first action signal.

Abstract: An apparatus, processor, and method for synchronizing trace data. A processor includes multiple cores, and each core operates at a different local clock frequency. A global clock is distributed to each core, and a timestamp is generated using the global clock and the local clock. The timestamp and a local clock saturation value are included in each trace entry, and the local clock saturation value is equal to the ratio between the local clock and the global clock. The trace entries from separate cores are time-correlated in a post-processing phase based on the timestamp and local clock saturation values.

Abstract: An integrated circuit with multiple clock domain tracing capability includes a debug module including a global time stamp counter for counting pulses of a reference clock signal to provide a global time stamp, a first granularity counter for counting pulses of a first clock signal to provide a first granularity count, a second granularity counter for counting pulses of a second clock signal to provide a second granularity count and a trace cache buffer for selectively storing in a first partition the global time stamp, the first granularity count, and first data synchronous to the first clock signal, and for selectively storing in a second partition the global time stamp, the second granularity count, and second data synchronous to the second clock signal.

Abstract: A method and apparatus for distributed on-chip debug triggering is presented. A first bus includes a plurality of lines and a debugging state machine configurable to monitor the plurality of lines of the first bus. One or more nodes are configurable to detect triggering events and provide, in response to detecting one or more triggering events, signals to the debugging state machine using a first subset of the plurality of lines that is allocated to the node(s).

Abstract: An embodiment of an electronic system includes a first electronic module, a second electronic module, a first debug circuit integrated with the first electronic module, a second debug circuit integrated with the second electronic module, and a communications interface between the first debug circuit and the second debug circuit. The first debug circuit is configured to determine that a triggering event has occurred, and to produce a first cross trigger signal on the communications interface in response to determining that the triggering event has occurred. The second debug circuit is configured to detect the first cross trigger signal on the communications interface, and to perform an action in response to detecting the first cross trigger signal.

Abstract: A system and method for efficiently debugging an integrated circuit with on-die hardware. A processor core includes an on-die debug state machine (DSM). The DSM includes multiple programmable storage elements for storing parameter values corresponding to multiple contexts. Each context is associated with a given one of multiple instruction sequences, such as at least threads and power-performance states. The DSM detects a sequence identifier (ID) and selects a context based on the sequence ID. The corresponding parameter values are used by transition conditions (triggers) and taken debug actions in a finite state machine (FSM) within the DSM. Each state and transition in the FSM is used by each one of the multiple contexts. The programmable DSM shares many resources, rather than replicating them, while being used for multiple sequences.

Abstract: An integrated circuit with debug capability includes a first packer and synchronizer to combine a multiple number of values of a first trigger signal received from a first circuit to form a first packed trigger signal and to output a synchronized first packed trigger signal in response to a trigger clock signal, the first trigger signal being synchronous with a first source clock signal, a first logic gate to provide a first output trigger signal indicative of whether any of the first multiple number of values of the first trigger signal in the first synchronized packed trigger signal is in a first state, and a debug state machine responsive to the first output trigger signal to selectively provide a first action signal.

Abstract: An integrated circuit with multiple clock domain tracing capability includes a debug module including a global time stamp counter for counting pulses of a reference clock signal to provide a global time stamp, a first granularity counter for counting pulses of a first clock signal to provide a first granularity count, a second granularity counter fir counting pulses of a second clock signal to provide a second granularity count and a trace cache buffer for selectively storing in a first partition the global time stamp, the first granularity count, and first data synchronous to the first clock signal, and for selectively storing in a second partition the global time stamp, the second granularity count, and second data synchronous to the second clock signal.

Abstract: The present invention provides a method and apparatus for dynamically configuring debug triggering patterns. One example embodiment of the method includes comparing values of bits received on a first subset of a plurality of lines of a bus with a first pattern of bits and capturing values of bits received on a second subset of the plurality of lines of the bus in response to the comparison indicating that the values of the bits received on the first subset of the lines match the first pattern of bits. The exemplary embodiment of the method also includes defining a second pattern for triggering a debug action using the captured values.

Abstract: An apparatus, processor, and method for synchronizing trace data. A processor includes multiple cores, and each core operates at a different local clock frequency. A global clock is distributed to each core, and a timestamp is generated using the global clock and the local clock. The timestamp and a local clock saturation value are included in each trace entry, and the local clock saturation value is equal to the ratio between the local clock and the global clock. The trace entries from separate cores are time-correlated in a post-processing phase based on the timestamp and local clock saturation values.

Abstract: An embodiment of an electronic system includes a first electronic module, a second electronic module, a first debug circuit integrated with the first electronic module, a second debug circuit integrated with the second electronic module, and a communications interface between the first debug circuit and the second debug circuit. The first debug circuit is configured to determine that a triggering event has occurred, and to produce a first cross trigger signal on the communications interface in response to determining that the triggering event has occurred. The second debug circuit is configured to detect the first cross trigger signal on the communications interface, and to perform an action in response to detecting the first cross trigger signal.

Abstract: Embodiments include methods for performing various operations in a computing system that includes an electronic module and a debug circuit. The method includes programming the debug circuit to monitor for pre-selected triggers produced by the computing system, and to perform actions in response to detecting the pre-select triggers. For example, in response to various pre-selected triggers, the debug circuit may, among other things: perform state transitions and log information indicating whether or not the state transitions were performed; monitor various signals when the debug circuit has determined that a test escape has occurred; and/or perform one or more actions that initiate stopping one or more clocks in response to certain pre-selected triggers.

Abstract: In an electronic system that includes a plurality of electronic modules and a plurality of debug circuits, each of which is integrated with one of the plurality of electronic modules, a method for performing debug operations is performed by the plurality of debug circuits. The method includes each of the plurality of debug circuits producing a first cross trigger signal on a communications interface between the plurality of debug circuits, where the first cross trigger signal indicates that a triggering event has not occurred. The method further includes each of the plurality of debug circuits determining whether the triggering event has occurred, and in response to determining that the triggering event has occurred, each of the plurality of debug circuits producing a second cross trigger signal on the communications interface, which indicates that the triggering event has occurred.

Abstract: Systems, methods, and other embodiments associated with synchronizing link delay is provided. In one example system, a system for synchronizing signal communication between a first electronic component and a second electronic component connected by one or more serial communication links comprises an offset logic configured to apply a selected offset to signal transmissions to cause a unidirectional delay between the first and the second electronic components to be synchronized for both directions of signal transmissions. A synchronization logic is configured to determine the uni-directional delay for signal transmissions between the first and second electronic components and configured to control the offset logic to apply the selected offset.

Abstract: A fully mirrored memory system includes at least one split memory bus, with each portion of the split memory bus having active memory and mirror memory. Each portion of the memory bus transfers a portion of the data for a memory transaction. If a memory unit is determined to be defective, one portion of the memory bus may be inactivated for hot swapping of memory, and the system can continue to operate using an active portion of the memory bus.

Abstract: Systems, methods, and other embodiments associated with a repeatable communication system are disclosed. One example system for receiving signals from an electronic component over a plurality of point-to-point communication links comprises a repeatability logic operably connected to each of the plurality of point-to-point communication links and configured to apply a delay offset to the signals received to compensate for frequency changes in signal transmissions over the plurality of point-to-point communication links.

Abstract: A double data rate memory controller is provided with a plurality of data and strobe pads, means for receiving data and strobe signals via said pads at 1x double data rate memory speed, and means for receiving data and strobe signals via said pads at Mx double data rate memory speed (M2).