Patents by Inventor Eric M. Rentschler

Eric M. Rentschler has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5793660
    Abstract: A circuit that finds m mod n may be obtained by creating the trial differences m-n, m-2n, m-3n, m-4n . . . , up to a limit determined by the sizes of m and n. The trial differences thus produced are examined in the order given to find the last one thereof that is non-negative. This examination involves only sign bits and a priority encoder. The magnitude portions of the various trial differences are applied as inputs to a first MUX whose selection is controlled by the priority encoder. The trial difference selected by the first MUX is applied as an input to a second MUX, whose other inputs are m itself, and zero. A separate initial comparison is performed between m and n, and controls what appears at the output of the second MUX. If n>m then the value of m appears at the output of the second MUX; if n=m or n=1 then zero appears; otherwise, m >n and it is the output from the first MUX that appears as the output of the second MUX. The output of the second MUX is m mod n.
    Type: Grant
    Filed: April 14, 1997
    Date of Patent: August 11, 1998
    Assignee: Hewlett-Packard Company
    Inventor: Eric M. Rentschler
  • Patent number: 5671373
    Abstract: An apparatus and method for transferring data between first and second circuit blocks of a computer graphics system are provided. The first and second circuit blocks are interconnected by a data bus having n bits. The apparatus includes a circuit in the first circuit block for sequentially transmitting data words from the first circuit block to a second circuit block on the data bus. The data words include one or more long data words having more than n bits. The apparatus further includes a register in the first circuit block for storing bits of the long data words in excess of n bits, and a controller in the first circuit block for loading the bits of the long data words in excess of n bits into the register and for combining the bits of the long data words stored in the register into a composite data word for transmission to the second circuit block. The composite data word may include a short data word having less than n bits.
    Type: Grant
    Filed: June 8, 1995
    Date of Patent: September 23, 1997
    Assignee: Hewlett-Packard Company
    Inventors: Bryan G. Prouty, Eric M. Rentschler