Abstract: A new zSeries floating-point unit has a fused multiply-add dataflow capable of supporting two architectures and fused MULTIPLY and ADD and Multiply and SUBTRACT in both RRF and RXF formats for the fused functions. Both binary and hexadecimal floating-point instructions are supported for a total of 6 formats. The floating-point unit is capable of performing a multiply-add instruction for hexadecimal or binary every cycle with a latency of 5 cycles. This supports two architectures with two internal formats with their own biases. This has eliminated format conversion cycles and has optimized the width of the dataflow. The unit is optimized for both hexadecimal and binary floating-point architecture supporting a multiply-add/subtract per cycle.

Abstract: A method, system, and computer program product are provided for prioritizing transactions. A processor in a computing environment initiates the execution of a transaction. The processor includes a transactional core, and the execution of the transaction is performed by the transactional core. The processor obtains concurrent with the execution of the transaction by the transactional core, an indication of a conflict between the transaction and at least one other transaction being executed by an additional core in the computing environment. The processor determines if the transactional core includes an indicator and based on determining that the transactional core includes an indicator, the processor ignores the conflict and utilizing the transactional core to complete executing the transaction.

Abstract: In a transactional memory environment including a first processor and one or more additional processors, a computer-implemented method includes identifying a memory location and sending a probe request from the first processor to the additional processors. The probe request includes the memory location. The computer implemented method further includes generating, by each additional processor, an indication including whether the memory location is in use for a transaction by the additional processor. The computer-implemented method further includes sending the indication from each additional processor to the first processor and proceeding, by the first processor, based on the indication.

Abstract: A computer system includes transactional memory to implement a nested transaction. The computer system generates a plurality of speculative identification numbers (IDs), identifies at least one of a software thread executed by a hardware processor and a memory operation performed in accordance with an application code. The computer system assigns at least one speculative cache version to a requested transaction based on a corresponding software thread. The speculative ID of the corresponding software thread identifies the speculative cache version. The computer system also identifies a nested transaction in the memory unit, assigns a cache version to the nested transaction, detects a conflict with the nested transaction, determines a conflicted nesting level of the nested transaction, and determines a cache version corresponding to the conflicted nesting level. The computer system also invalidates the cache version corresponding to the conflicted nesting level.

Abstract: Embodiments relate to a system operation queue for a transaction. An aspect includes determining whether a system operation is part of an in-progress transaction of a central processing unit (CPU). Another aspect includes based on determining that the system operation is part of the in-progress transaction, storing the system operation in a system operation queue corresponding to the in-progress transaction. Yet another aspect includes, based on the in-progress transaction ending, processing the system operation in the system operation queue.

Abstract: Embodiments relate to non-default instruction handling within a transaction. An aspect includes entering a transaction, the transaction comprising a first plurality of instructions and a second plurality of instructions, wherein a default manner of handling of instructions in the transaction is one of atomic and non-atomic. Another aspect includes encountering a non-default specification instruction in the transaction, wherein the non-default specification instruction comprises a single instruction that specifies the second plurality of instructions of the transaction for handling in a non-default manner comprising one of atomic and non-atomic, wherein the non-default manner is different from the default manner. Another aspect includes handling the first plurality of instructions in the default manner. Yet another aspect includes handling the second plurality of instructions in the non-default manner.

Abstract: Machine instructions, referred to herein as a long Convert from Zoned instruction (CDZT) and extended Convert from Zoned instruction (CXZT), are provided that read EBCDIC or ASCII data from memory, convert it to the appropriate decimal floating point format, and write it to a target floating point register or floating point register pair. Further, machine instructions, referred to herein as a long Convert to Zoned instruction (CZDT) and extended Convert to Zoned instruction (CZXT), are provided that convert a decimal floating point (DFP) operand in a source floating point register or floating point register pair to EBCDIC or ASCII data and store it to a target memory location.

Abstract: A Vector Floating Point Test Data Class Immediate instruction is provided that determines whether one or more elements of a vector specified in the instruction are of one or more selected classes and signs. If a vector element is of a selected class and sign, an element in an operand of the instruction corresponding to the vector element is set to a first defined value, and if the vector element is not of the selected class and sign, the operand element corresponding to the vector element is set to a second defined value.

Abstract: Machine instructions, referred to herein as a long Convert from Zoned instruction (CDZT) and extended Convert from Zoned instruction (CXZT), are provided that read EBCDIC or ASCII data from memory, convert it to the appropriate decimal floating point format, and write it to a target floating point register or floating point register pair. Further, machine instructions, referred to herein as a long Convert to Zoned instruction (CZDT) and extended Convert to Zoned instruction (CZXT), are provided that convert a decimal floating point (DFP) operand in a source floating point register or floating point register pair to EBCDIC or ASCII data and store it to a target memory location.

Abstract: A method for implementing a programmable linear feedback shift register instruction, the method includes obtaining, by a processor, the machine instruction for execution, the machine instruction includes a first input operand indicating the current value of a shift register, wherein the shift register includes a data bit for each of a plurality of cells, a second input operand indicating a first sub-set of cells from the plurality of cells, and a logical operation specifier field indicating a logical operation to perform on the first and second input operands. Additionally, executing the machine instruction includes performing the logical operation based on the first input operand, the second input operand, and the logical operation specifier field, and generating an output operand by shifting the current value of the shift register to vacate a cell of the shift register and inserting an output value of the logical operation into the vacated cell of the shift register.

Abstract: A Spin Loop Delay instruction. The instruction has a field associated therewith that indicates one or more conditions to be checked. Dispatching of the instruction is initially delayed. The instruction is subsequently dispatched based on a timeout, provided the instruction has not been previously dispatched based on meeting at least one condition of the one or more conditions to be checked.

Abstract: One or more transactions may request or be assigned tokens within a transactional memory environment. A transaction may be created by at least one thread. A first transaction that includes a first token type may be received. A request may be received for a for a potential conflict check between the first transaction and a second transaction. In response to receiving the transaction potential conflict check, the first transaction and the second transaction are determined to be conflicting or not conflicting. The second transaction is assigned a token type in response to the determination of the transaction potential conflict check between the first transaction and the second transaction.

Abstract: One or more transactions may request or be assigned tokens within a transactional memory environment. A transaction may be created by at least one thread. A first transaction that includes a first token type may be received. A request may be received for a for a potential conflict check between the first transaction and a second transaction. In response to receiving the transaction potential conflict check, the first transaction and the second transaction are determined to be conflicting or not conflicting. The second transaction is assigned a token type in response to the determination of the transaction potential conflict check between the first transaction and the second transaction.

Abstract: A Spin Loop Delay instruction. The instruction has a field associated therewith that indicates one or more conditions to be checked. Dispatching of the instruction is initially delayed. The instruction is subsequently dispatched based on a timeout, provided the instruction has not been previously dispatched based on meeting at least one condition of the one or more conditions to be checked.

Abstract: A new zSeries floating-point unit has a fused multiply-add dataflow capable of supporting two architectures and fused MULTIPLY and ADD and Multiply and SUBTRACT in both RRF and RXF formats for the fused functions. Both binary and hexadecimal floating-point instructions are supported for a total of 6 formats. The floating-point unit is capable of performing a multiply-add instruction for hexadecimal or binary every cycle with a latency of 5 cycles. This supports two architectures with two internal formats with their own biases. This has eliminated format conversion cycles and has optimized the width of the dataflow. The unit is optimized for both hexadecimal and binary floating-point architecture supporting a multiply-add/subtract per cycle.

Abstract: A transactional memory execution environment receives a first request from a first transaction to access a cache line. A first request is received from a first transaction to access a cache line. The cache line is determined to be used by a second transaction. The first transaction and the second transaction opt-in to a transaction potential conflict check. The transaction potential conflict check determines if the first transaction and the second transaction are in a conflicting coherent state. The conflicting coherent state occurs when the first transaction is modifying the cache line used by the second transaction. The first transaction is allowed access to the cache line without aborting the second transaction in response to a determination that the first transaction and the second transaction are compatible from the transaction potential conflict check.

Abstract: An instruction to perform a shift and divide operation is executed. The executing includes shifting a value in a specified direction by a selected amount to provide a dividend, the selected amount being user-defined. The dividend is divided by a divisor to obtain a quotient. At least a subset of the quotient is selected as a result. The result is to be used in processing within the computing environment.

Abstract: A transactional memory execution environment receives a first request from a first transaction to access a cache line. A first request is received from a first transaction to access a cache line. The cache line is determined to be used by a second transaction. The first transaction and the second transaction opt-in to a transaction potential conflict check. The transaction potential conflict check determines if the first transaction and the second transaction are in a conflicting coherent state. The conflicting coherent state occurs when the first transaction is modifying the cache line used by the second transaction. The first transaction is allowed access to the cache line without aborting the second transaction in response to a determination that the first transaction and the second transaction are compatible from the transaction potential conflict check.

Abstract: An instruction to perform a shift and divide operation is executed. The executing includes shifting a value in a specified direction by a selected amount to provide a dividend, the selected amount being user-defined. The dividend is divided by a divisor to obtain a quotient. At least a subset of the quotient is selected as a result. The result is to be used in processing within the computing environment.

Abstract: A round-for-reround mode (preferably in a BID encoded Decimal format) of a floating point instruction prepares a result for later rounding to a variable number of digits by detecting that the least significant digit may be a 0, and if so changing it to 1 when the trailing digits are not all 0. A subsequent reround instruction is then able to round the result to any number of digits at least 2 fewer than the number of digits of the result. An optional embodiment saves a tag indicating the fact that the low order digit of the result is 0 or 5 if the trailing bits are non-zero in a tag field rather than modify the result. Another optional embodiment also saves a half-way-and-above indicator when the trailing digits represent a decimal with a most significant digit having a value of 5. An optional subsequent reround instruction is able to round the result to any number of digits fewer or equal to the number of digits of the result using the saved tags.