Patents by Inventor Eric Vann

Eric Vann has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • AVALANCHE ROBUST LDMOS
    Publication number: 20190312139
    Abstract: A semiconductor device includes an active region formed over a substrate. The active region includes a FET and a diode. The FET includes one or more FET fingers. Each FET finger includes a FET source region, a FET drain region, and a lateral FET gate electrode. The diode includes one or more diode fingers. Each of the diode fingers includes a diode anode region electrically coupled to the FET source region, a diode cathode region electrically coupled to the FET drain region, and a lateral diode gate electrode electrically coupled to the diode anode region and electrically isolated from the lateral FET gate electrode. The FET fingers are active fingers of the semiconductor device and the diode fingers are dummy fingers of the semiconductor device. The diode is configured to clamp a maximum voltage developed across the FET drain region and the FET source region.
    Type: Application
    Filed: April 4, 2018
    Publication date: October 10, 2019
    Applicant: Silanna Asia Pte Ltd
    Inventors: Shanghui Larry Tu, Vadim Kushner, Eric Vann
  • Avalanche robust LDMOS
    Patent number: 10424661
    Abstract: A semiconductor device includes an active region formed over a substrate. The active region includes a FET and a diode. The FET includes one or more FET fingers. Each FET finger includes a FET source region, a FET drain region, and a lateral FET gate electrode. The diode includes one or more diode fingers. Each of the diode fingers includes a diode anode region electrically coupled to the FET source region, a diode cathode region electrically coupled to the FET drain region, and a lateral diode gate electrode electrically coupled to the diode anode region and electrically isolated from the lateral FET gate electrode. The FET fingers are active fingers of the semiconductor device and the diode fingers are dummy fingers of the semiconductor device. The diode is configured to clamp a maximum voltage developed across the FET drain region and the FET source region.
    Type: Grant
    Filed: April 4, 2018
    Date of Patent: September 24, 2019
    Assignee: Silanna Asia Pte Ltd
    Inventors: Shanghui Larry Tu, Vadim Kushner, Eric Vann