Patents by Inventor Erich F Haratsch

Erich F Haratsch has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10410736
    Abstract: An apparatus includes a memory and a controller. The memory may be configured to store data. The controller may be configured to process a plurality of input/output requests to a plurality of blocks of the memory that are not marked as bad on a block list, perform a code rate test that programs the plurality of blocks of the memory at three or more code rates of an error correction code scheme, and mark any of the plurality of blocks identified as bad during the code rate test on the block list.
    Type: Grant
    Filed: February 3, 2017
    Date of Patent: September 10, 2019
    Assignee: Seagate Technology LLC
    Inventors: Zhengang Chen, David Patmore, Yingji Ju, Erich F. Haratsch
  • Patent number: 10396817
    Abstract: A low-density parity-check decoder utilizes information about hard errors in a storage medium to identify bit locations to flip log-likelihood ratios while attempting to decode codewords. The decoder iteratively flips and saturates log-likelihood ratios for bits at hard error locations and re-decodes until a valid codeword is produced. The decoder also identifies variable nodes associated with trapping sets for iterative log-likelihood ratio bit flipping.
    Type: Grant
    Filed: December 5, 2016
    Date of Patent: August 27, 2019
    Assignee: Seagate Technology LLC
    Inventors: Zhengang Chen, Abdelhakim S. Alhussein, Erich F. Haratsch
  • Patent number: 10388368
    Abstract: Adaptive read reference voltage tracking techniques are provided that employ charge leakage mitigation. An exemplary device for use with multi-level memory cells, comprises a controller configured to: after a predefined time interval that approximates a settling time after a programming of the multi-level memory cells until a charge leakage of one or more of the multi-level memory cells has settled, determine a plurality of read reference voltages for the multi-level memory cells using a post-programming adaptive tracking algorithm; and employ the plurality of read reference voltages to read data from the multi-level memory cells. The reference voltage offsets are optionally determined based on a shift in the read reference voltages after the predefined time interval since the programming of the multi-level memory cells.
    Type: Grant
    Filed: October 31, 2017
    Date of Patent: August 20, 2019
    Assignee: Seagate Technology LLC
    Inventors: Ludovic Danjean, Sundararajan Sankaranarayanan, Erich F. Haratsch
  • Patent number: 10388385
    Abstract: Channel information and channel conditions determined by an Offline Tracking process are used to determine whether or not an adjustment to the read reference voltage can be avoided altogether without detrimentally affecting performance, or, alternatively, to determine a precision with which a read reference voltage adjustment should be made. If it is determined based on the channel conditions that a read reference voltage adjustment can be avoided altogether, read performance is improved by reducing the probability that a read reference voltage adjustment needs to be made during normal read operations. If it is determined based on the channel conditions that a read reference voltage adjustment needs to be made with a particular precision, the read reference voltage is so adjusted. This latter approach is advantageous in that relatively fewer adjustments will be made during normal read operations.
    Type: Grant
    Filed: February 23, 2017
    Date of Patent: August 20, 2019
    Assignee: Seagate Technology LLC
    Inventors: Zhengang Chen, Erich F. Haratsch, Sundararajan Sankaranarayanan
  • Publication number: 20190245557
    Abstract: A data processing system includes a likelihood input operable to receive encoded data, a decoder operable to apply a decoding algorithm to likelihood values for the received encoded data and to yield a decoded output, and a decoder input initialization circuit operable to generate new decoder input values based in part on the likelihood values for the received encoded data after the likelihood values for the received encoded data have failed to converge in the decoder.
    Type: Application
    Filed: April 19, 2019
    Publication date: August 8, 2019
    Applicant: SEAGATE TECHNOLOGY LLC
    Inventors: Sundarajan Sankaranarayanan, AbdelHakim S. Alhussien, Erich F. Haratsch, Earl Cohen
  • Patent number: 10353622
    Abstract: Systems and methods for internal copy-back with read-verify are described. In one embodiment, a storage device includes a controller to select a first single level cell (SLC) page of a plurality of SLC pages on the storage device to transfer to a triple level cell (TLC) page. The controller, in conjunction with an error correcting code (ECC) decoder, read-verifies the first SLC page. Read-verifying the first SLC page includes reading the first SLC page to an internal page buffer, decoding the first SLC page read into the internal page buffer, determining a number of errors contained in the first SLC page based at least in part on the decoding, and verifying whether the number of errors contained in the first SLC page satisfies an error threshold. The controller transfers the first SLC page to the TLC page according to a result of read-verifying the first SLC page.
    Type: Grant
    Filed: March 2, 2017
    Date of Patent: July 16, 2019
    Assignee: SEAGATE TECHNOLOGY LLC
    Inventors: Erich F. Haratsch, Zhengang Chen, Stephen Hanna, Abdelhakim Alhussien
  • Patent number: 10347343
    Abstract: Methods and apparatus are provided for adaptive read threshold voltage tracking with separate characterization on each side of a voltage distribution about a distribution mean. A read threshold voltage for a memory is adjusted by determining statistical characteristics of two adjacent memory levels based at least in part on a type of statistical distribution of the memory levels and a distribution of data values read from cells using a plurality of read threshold voltages, wherein the statistical characteristics of the two adjacent memory levels are characterized independently on two sides about at least one mean of the statistical distribution; computing an adjusted read threshold voltage associated with the two adjacent memory levels by using the statistical characteristics of the two adjacent memory levels; and updating the read threshold voltage based on the adjusted read threshold voltage. The adjustment is optionally performed responsive to one or more read errors.
    Type: Grant
    Filed: October 30, 2015
    Date of Patent: July 9, 2019
    Assignee: Seagate Technology LLC
    Inventors: Sundararajan Sankaranarayanan, Erich F. Haratsch
  • Patent number: 10303402
    Abstract: A data storage device includes at least one data storage medium and a controller that is operably coupled to the at least one data storage medium. The controller receives the bit stream in a data storage device and performs a first level of compression on the received bit stream to obtain a symbol frame including a plurality of symbols. The controller encodes an initial portion of the plurality of symbols contained in the symbol frame by a fixed encoding scheme. The controller also collects statistics for the initial portion of the symbol frame. The controller then selects at least one data compression algorithm based on the collected statistics. The controller then performs compression encoding on a remaining portion of the symbol frame with the selected at least one data compression algorithm.
    Type: Grant
    Filed: August 2, 2016
    Date of Patent: May 28, 2019
    Assignee: SEAGATE TECHNOLOGY LLC
    Inventors: Hongmei Xie, Zhengang Chen, Bijan Eskandari-Gharnin, Erich F. Haratsch
  • Patent number: 10298263
    Abstract: A data processing system includes a likelihood input operable to receive encoded data, a decoder operable to apply a decoding algorithm to likelihood values for the received encoded data and to yield a decoded output, and a decoder input initialization circuit operable to generate new decoder input values based in part on the likelihood values for the received encoded data after the likelihood values for the received encoded data have failed to converge in the decoder.
    Type: Grant
    Filed: March 18, 2014
    Date of Patent: May 21, 2019
    Assignee: SEAGATE TECHNOLOGY LLC
    Inventors: Sundararajan Sankaranarayanan, AbdelHakim S. Alhussien, Erich F. Haratsch, Earl Cohen
  • Patent number: 10298264
    Abstract: Systems and method relating generally to solid state memory, and more particularly to systems and methods for generated data from a solid state memory. A data processing system includes a solid state memory device, a soft data generation circuit operable to receive multiple instances of an element of a read data set accessed from the solid state memory device, and access a scramble compensating extended look up table using the multiple instances of the element to receive corresponding soft data, and a data decoder circuit operable to yield a decoded output from the soft data.
    Type: Grant
    Filed: April 9, 2018
    Date of Patent: May 21, 2019
    Assignee: SEAGATE TECHNOLOGY LLC
    Inventors: Zhengang Chen, Yunxiang Wu, Erich F. Haratsch
  • Patent number: 10290358
    Abstract: Read threshold voltage tracking techniques are provided for multiple dependent read threshold voltages using syndrome weights.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: May 14, 2019
    Assignee: Seagate Technology LLC
    Inventors: AbdelHakim S. Alhussien, Sundararajan Sankaranarayanan, Erich F. Haratsch
  • Publication number: 20190130966
    Abstract: Adaptive read reference voltage tracking techniques are provided that employ charge leakage mitigation. An exemplary device comprises a controller configured to: determine at least one reference voltage offset for a plurality of read reference voltages, wherein the at least one reference voltage offset is determined based on a shift in one or more of the read reference voltages over time; shift the plurality of read reference voltages using the at least one reference voltage offset; and employ the plurality of read reference voltages shifted by the at least one reference voltage offset to read data from the multi-level memory cells. The shifting step is optionally performed after a predefined time interval that approximates a settling time after a programming of the multi-level memory cells until a charge leakage of the multi-level memory cells has settled.
    Type: Application
    Filed: October 31, 2017
    Publication date: May 2, 2019
    Applicant: Seagate Technology LLC
    Inventors: Ludovic Danjean, Sundararajan Sankaranarayanan, Erich F. Haratsch
  • Publication number: 20190130967
    Abstract: Adaptive read reference voltage tracking techniques are provided that employ charge leakage mitigation. An exemplary device for use with multi-level memory cells, comprises a controller configured to: after a predefined time interval that approximates a settling time after a programming of the multi-level memory cells until a charge leakage of one or more of the multi-level memory cells has settled, determine a plurality of read reference voltages for the multi-level memory cells using a post-programming adaptive tracking algorithm; and employ the plurality of read reference voltages to read data from the multi-level memory cells. The reference voltage offsets are optionally determined based on a shift in the read reference voltages after the predefined time interval since the programming of the multi-level memory cells.
    Type: Application
    Filed: October 31, 2017
    Publication date: May 2, 2019
    Applicant: Seagate Technology LLC
    Inventors: Ludovic Danjean, Sundararajan Sankaranarayanan, Erich F. Haratsch
  • Patent number: 10276247
    Abstract: Methods and apparatus are provided for read retry operations that estimate written data based on syndrome weights. One method comprises reading a codeword from a memory multiple times using multiple read reference voltages; obtaining a syndrome weight for each of the readings of the codeword; identifying a given reading of the codeword having a substantially minimum syndrome weight; and estimating a written value of the codeword based on the given reading. Two cell voltage probability distributions of cell voltages are optionally calculated for each possible cell state of the memory, based on the estimated written value and plurality of readings of the codeword. The cell voltage probability distributions are used to (i) dynamically select log likelihood ratio values for a failing page, (ii) determine a read reference voltage that gives a desired log likelihood ratio value, or (iii) dynamically select log likelihood ratio values for the page populations associated with the distributions.
    Type: Grant
    Filed: July 8, 2016
    Date of Patent: April 30, 2019
    Assignee: Seagate Technology LLC
    Inventors: AbdelHakim S. Alhussien, Sundararajan Sankaranarayanan, Thuy Van Nguyen, Ludovic Danjean, Erich F. Haratsch
  • Patent number: 10276233
    Abstract: Adaptive read reference voltage tracking techniques are provided that employ charge leakage mitigation. An exemplary device comprises a controller configured to: determine at least one reference voltage offset for a plurality of read reference voltages, wherein the at least one reference voltage offset is determined based on a shift in one or more of the read reference voltages over time; shift the plurality of read reference voltages using the at least one reference voltage offset; and employ the plurality of read reference voltages shifted by the at least one reference voltage offset to read data from the multi-level memory cells. The shifting step is optionally performed after a predefined time interval that approximates a settling time after a programming of the multi-level memory cells until a charge leakage of the multi-level memory cells has settled.
    Type: Grant
    Filed: October 31, 2017
    Date of Patent: April 30, 2019
    Assignee: Seagate Technology LLC
    Inventors: Ludovic Danjean, Sundararajan Sankaranarayanan, Erich F. Haratsch
  • Publication number: 20190122726
    Abstract: Techniques are provided for adaptive read threshold voltage tracking with gap estimation between default read threshold voltages. A read threshold voltage for a memory is adjusted by estimating a gap between two adjacent default read threshold voltages using binary data from the memory, wherein the gap is estimated using statistical characteristics of at least one of two adjacent memory levels of the memory; computing an adjusted read threshold voltage associated with the two adjacent memory levels by using the statistical characteristics of the two adjacent memory levels and the gap; and updating the read threshold voltage with the adjusted read threshold voltage. Pages of the memory are optionally read at multiple read threshold offset locations to obtain disparity statistics, which can be used to estimate mean and/or standard deviation values for a given memory level. The gap is optionally estimated using the mean and/or standard deviation values.
    Type: Application
    Filed: December 12, 2018
    Publication date: April 25, 2019
    Applicant: Seagate Technology LLC
    Inventors: Sundararajan Sankaranarayanan, Erich F. Haratsch
  • Patent number: 10263640
    Abstract: Method and apparatus for decoding data. In some embodiments, an LDPC decoder has a variable node circuit (VNC) with a plurality of variable nodes configured to store bit reliability values of m-bit code bits. A check node circuit (CNC) has a plurality of check nodes configured to perform parity check operations upon n-bit messages from the VNC. Each n-bit message is formed from a combination of the bit reliability values and stored messages from the check nodes. A pre-saturation compensation circuit is configured to maintain a magnitude of each n-bit message received by the CNC below a saturation limit comprising the maximum value that can be expressed using p bits, with p less than n and each of the n-bit messages received by the CNC having a different magnitude. The pre-saturation compensation circuit may apply different scaling and/or bias factors to the n-bit messages over different decoding iterations.
    Type: Grant
    Filed: April 4, 2017
    Date of Patent: April 16, 2019
    Assignee: Seagate Technology LLC
    Inventors: Ivana Djurdjevic, Ara Patapoutian, Zheng Wang, AbdelHakim Alhussien, Sundararajan Sankaranarayanan, Ludovic Danjean, Erich F. Haratsch
  • Patent number: 10192614
    Abstract: Methods and apparatus are provided for adaptive read threshold voltage tracking with gap estimation between default read threshold voltages. A read threshold voltage for a memory is adjusted by estimating a gap between two adjacent default read threshold voltages; determining statistical characteristics of two adjacent memory levels based at least in part on a type of statistical distribution of the memory levels, a distribution of data values read from one or more cells using a plurality of read threshold voltages and the gap; computing an adjusted read threshold voltage associated with the two adjacent memory levels by using the statistical characteristics of the two adjacent memory levels; and updating the read threshold voltage with the adjusted read threshold voltage. The adjustment is optionally performed responsive to one or more read errors.
    Type: Grant
    Filed: December 8, 2015
    Date of Patent: January 29, 2019
    Assignee: Seagate Technology LLC
    Inventors: Sundararajan Sankaranarayanan, Erich F. Haratsch
  • Patent number: 10180868
    Abstract: Adaptive read threshold voltage tracking techniques are provided that employ bit error rate estimation based on a non-linear syndrome weight mapping. An exemplary device comprises a controller configured to determine a bit error rate for at least one of a plurality of read threshold voltages in a memory using a non-linear mapping of a syndrome weight to the bit error rate for the at least one of the plurality of read threshold voltages.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: January 15, 2019
    Assignee: Seagate Technology LLC
    Inventors: AbdelHakim S. Alhussien, Sundararajan Sankaranarayanan, Erich F. Haratsch
  • Patent number: 10177787
    Abstract: An apparatus having an interface and a control circuit is disclosed. The interface may be configured to process a plurality of read/write operations to/from a memory. The control circuit may be configured to (i) access information that characterizes a plurality of trapping sets of a low-density parity check code in response to receiving data, (ii) encode the data using the low-density parity check code to generate a codeword and (iii) write the codeword in the memory. The generation of the codeword may include at least one of a shortening and a puncturing of a plurality of bits in the codeword. The plurality of bits may be selected based on the information that characterizes the plurality of trapping sets. The bits selected generally reduce a probability that an error correction of the codeword after the codeword is read from the memory fails due to the plurality of trapping sets.
    Type: Grant
    Filed: September 17, 2015
    Date of Patent: January 8, 2019
    Assignee: SEAGATE TECHNOLOGY LLC
    Inventors: Ludovic Danjean, Sundararajan Sankaranarayanan, Ivana Djurdjevic, AbdelHakim Alhussien, Erich F. Haratsch