Patents by Inventor Erik Nino Tolentino
Erik Nino Tolentino has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240072009Abstract: Implementations of semiconductor packages may include one or more die coupled over a substrate, an electrically conductive spacer coupled over the substrate, and a clip coupled over and to the one or more die and the electrically conductive spacer. The clip may electrically couple the one or more die and the electrically conductive spacer.Type: ApplicationFiled: October 19, 2023Publication date: February 29, 2024Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Chee Hiong CHEW, Erik Nino TOLENTINO, Vemmond Jeng Hung NG, Shutesh KRISHNAN
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Patent number: 11830856Abstract: Implementations of semiconductor packages may include one or more die coupled over a substrate, an electrically conductive spacer coupled over the substrate, and a clip coupled over and to the one or more die and the electrically conductive spacer. The clip may electrically couple the one or more die and the electrically conductive spacer.Type: GrantFiled: January 17, 2020Date of Patent: November 28, 2023Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Chee Hiong Chew, Erik Nino Tolentino, Vemmond Jeng Hung Ng, Shutesh Krishnan
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Patent number: 11791288Abstract: Implementations of methods of forming a plurality of reinforced die may include forming a plurality of die on a substrate and patterning a metal gang frame to form a plurality of metal plates. The plurality of metal plates may correspond to the plurality of die. The method may include coupling the metal gang frame over the plurality of die and singulating the plurality of die. Each die of the plurality of die may include the corresponding metal plate from the plurality of metal plates coupled over the plurality of die.Type: GrantFiled: April 27, 2022Date of Patent: October 17, 2023Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Chee Hiong Chew, Erik Nino Tolentino, Yusheng Lin, Swee Har Khor
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Publication number: 20220254734Abstract: Implementations of methods of forming a plurality of reinforced die may include forming a plurality of die on a substrate and patterning a metal gang frame to form a plurality of metal plates. The plurality of metal plates may correspond to the plurality of die. The method may include coupling the metal gang frame over the plurality of die and singulating the plurality of die. Each die of the plurality of die may include the corresponding metal plate from the plurality of metal plates coupled over the plurality of die.Type: ApplicationFiled: April 27, 2022Publication date: August 11, 2022Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Chee Hiong CHEW, Erik Nino TOLENTINO, Yusheng LIN, Swee Har KHOR
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Patent number: 11348878Abstract: Implementations of methods of forming a plurality of reinforced die may include forming a plurality of die on a substrate and patterning a metal gang frame to form a plurality of metal plates. The plurality of metal plates may correspond to the plurality of die. The method may include coupling the metal gang frame over the plurality of die and singulating the plurality of die. Each die of the plurality of die may include the corresponding metal plate from the plurality of metal plates coupled over the plurality of die.Type: GrantFiled: May 28, 2020Date of Patent: May 31, 2022Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Erik Nino Tolentino, Chee Hiong Chew, Yusheng Lin, Swee Har Khor
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Publication number: 20200294935Abstract: Implementations of methods of forming a plurality of reinforced die may include forming a plurality of die on a substrate and patterning a metal gang frame to form a plurality of metal plates. The plurality of metal plates may correspond to the plurality of die. The method may include coupling the metal gang frame over the plurality of die and singulating the plurality of die. Each die of the plurality of die may include the corresponding metal plate from the plurality of metal plates coupled over the plurality of die.Type: ApplicationFiled: May 28, 2020Publication date: September 17, 2020Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Erik Nino TOLENTINO, Chee Hiong CHEW, Yusheng LIN, Swee Har KHOR
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Publication number: 20200286865Abstract: Implementations of semiconductor packages may include one or more die coupled over a substrate, an electrically conductive spacer coupled over the substrate, and a clip coupled over and to the one or more die and the electrically conductive spacer. The clip may electrically couple the one or more die and the electrically conductive spacer.Type: ApplicationFiled: January 17, 2020Publication date: September 10, 2020Inventors: Chee Hiong CHEW, Erik Nino TOLENTINO, Vemmond Jeng Hung NG, Shutesh KRISHNAN
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Patent number: 10700018Abstract: Implementations of methods of forming a plurality of reinforced die may include forming a plurality of die on a substrate and patterning a metal gang frame to form a plurality of metal plates. The plurality of metal plates may correspond to the plurality of die. The method may include coupling the metal gang frame over the plurality of die and singulating the plurality of die. Each die of the plurality of die may include the corresponding metal plate from the plurality of metal plates coupled over the plurality of die.Type: GrantFiled: November 6, 2018Date of Patent: June 30, 2020Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Erik Nino Tolentino, Chee Hiong Chew, Yusheng Lin, Swee Har Khor
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Publication number: 20200161209Abstract: A power semiconductor package includes a first direct bonded copper (DBC) substrate having a plurality of connection traces on a first face of the first DBC substrate. A plurality of die are coupled to the connection traces, each die coupled to one of the connection traces at a first face of the die. A second DBC substrate includes connection traces on a first face of the second DBC substrate. A second face of each die is coupled to one of the connection traces of the first face of the second DBC substrate. A cavity between the first face of the first DBC substrate and the first face of the second DBC substrate is filled with an encapsulating compound. Terminal pins may be coupled to connection traces on the first face of the first DBC substrate. More than two DBC substrates may be stacked to form a stacked power semiconductor package.Type: ApplicationFiled: January 27, 2020Publication date: May 21, 2020Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Erik Nino TOLENTINO, Vemal Raja MANIKAM, Azhar ARIPIN
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Publication number: 20200144200Abstract: Implementations of methods of forming a plurality of reinforced die may include forming a plurality of die on a substrate and patterning a metal gang frame to form a plurality of metal plates. The plurality of metal plates may correspond to the plurality of die. The method may include coupling the metal gang frame over the plurality of die and singulating the plurality of die. Each die of the plurality of die may include the corresponding metal plate from the plurality of metal plates coupled over the plurality of die.Type: ApplicationFiled: November 6, 2018Publication date: May 7, 2020Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Erik Nino TOLENTINO, Chee Hiong CHEW, Yusheng LIN, Swee Har KHOR
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Patent number: 10546798Abstract: A power semiconductor package includes a first direct bonded copper (DBC) substrate having a plurality of connection traces on a first face of the first DBC substrate. A plurality of die are coupled to the connection traces, each die coupled to one of the connection traces at a first face of the die. A second DBC substrate includes connection traces on a first face of the second DBC substrate. A second face of each die is coupled to one of the connection traces of the first face of the second DBC substrate. A cavity between the first face of the first DBC substrate and the first face of the second DBC substrate is filled with an encapsulating compound. Terminal pins may be coupled to connection traces on the first face of the first DBC substrate. More than two DBC substrates may be stacked to form a stacked power semiconductor package.Type: GrantFiled: May 8, 2018Date of Patent: January 28, 2020Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Erik Nino Tolentino, Vernal Raja Manikam, Azhar Aripin
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Publication number: 20180261525Abstract: A power semiconductor package includes a first direct bonded copper (DBC) substrate having a plurality of connection traces on a first face of the first DBC substrate. A plurality of die are coupled to the connection traces, each die coupled to one of the connection traces at a first face of the die. A second DBC substrate includes connection traces on a first face of the second DBC substrate. A second face of each die is coupled to one of the connection traces of the first face of the second DBC substrate. A cavity between the first face of the first DBC substrate and the first face of the second DBC substrate is filled with an encapsulating compound. Terminal pins may be coupled to connection traces on the first face of the first DBC substrate. More than two DBC substrates may be stacked to form a stacked power semiconductor package.Type: ApplicationFiled: May 8, 2018Publication date: September 13, 2018Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Erik Nino TOLENTINO, Vemal Raja MANIKAM, Azhar ARIPIN
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Patent number: 9991185Abstract: A power semiconductor package includes a first direct bonded copper (DBC) substrate having a plurality of connection traces on a first face of the first DBC substrate. A plurality of die are coupled to the connection traces, each die coupled to one of the connection traces at a first face of the die. A second DBC substrate includes connection traces on a first face of the second DBC substrate. A second face of each die is coupled to one of the connection traces of the first face of the second DBC substrate. A cavity between the first face of the first DBC substrate and the first face of the second DBC substrate is filled with an encapsulating compound. Terminal pins may be coupled to connection traces on the first face of the first DBC substrate. More than two DBC substrates may be stacked to form a stacked power semiconductor package.Type: GrantFiled: April 18, 2017Date of Patent: June 5, 2018Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Erik Nino Tolentino, Vemal Raja Manikam, Azhair Aripin
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Publication number: 20170221792Abstract: A power semiconductor package includes a first direct bonded copper (DBC) substrate having a plurality of connection traces on a first face of the first DBC substrate. A plurality of die are coupled to the connection traces, each die coupled to one of the connection traces at a first face of the die. A second DBC substrate includes connection traces on a first face of the second DBC substrate. A second face of each die is coupled to one of the connection traces of the first face of the second DBC substrate. A cavity between the first face of the first DBC substrate and the first face of the second DBC substrate is filled with an encapsulating compound. Terminal pins may be coupled to connection traces on the first face of the first DBC substrate. More than two DBC substrates may be stacked to form a stacked power semiconductor package.Type: ApplicationFiled: April 18, 2017Publication date: August 3, 2017Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Erik Nino TOLENTINO, Vemal Raja MANIKAM, Azhair ARIPIN
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Patent number: 9659837Abstract: A power semiconductor package includes a first direct bonded copper (DBC) substrate having a plurality of connection traces on a first face of the first DBC substrate. A plurality of die are coupled to the connection traces, each die coupled to one of the connection traces at a first face of the die. A second DBC substrate includes connection traces on a first face of the second DBC substrate. A second face of each die is coupled to one of the connection traces of the first face of the second DBC substrate. A cavity between the first face of the first DBC substrate and the first face of the second DBC substrate is filled with an encapsulating compound. Terminal pins may be coupled to connection traces on the first face of the first DBC substrate. More than two DBC substrates may be stacked to form a stacked power semiconductor package.Type: GrantFiled: January 30, 2015Date of Patent: May 23, 2017Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Erik Nino Tolentino, Vemal Raja Manikam, Azhar Aripin
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Publication number: 20160225693Abstract: A power semiconductor package includes a first direct bonded copper (DBC) substrate having a plurality of connection traces on a first face of the first DBC substrate. A plurality of die are coupled to the connection traces, each die coupled to one of the connection traces at a first face of the die. A second DBC substrate includes connection traces on a first face of the second DBC substrate. A second face of each die is coupled to one of the connection traces of the first face of the second DBC substrate. A cavity between the first face of the first DBC substrate and the first face of the second DBC substrate is filled with an encapsulating compound. Terminal pins may be coupled to connection traces on the first face of the first DBC substrate. More than two DBC substrates may be stacked to form a stacked power semiconductor package.Type: ApplicationFiled: January 30, 2015Publication date: August 4, 2016Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Erik Nino Tolentino, Vemal Raja Manikam, Azhar Aripin