Patents by Inventor Erik Nino Tolentino

Erik Nino Tolentino has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220254734
    Abstract: Implementations of methods of forming a plurality of reinforced die may include forming a plurality of die on a substrate and patterning a metal gang frame to form a plurality of metal plates. The plurality of metal plates may correspond to the plurality of die. The method may include coupling the metal gang frame over the plurality of die and singulating the plurality of die. Each die of the plurality of die may include the corresponding metal plate from the plurality of metal plates coupled over the plurality of die.
    Type: Application
    Filed: April 27, 2022
    Publication date: August 11, 2022
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Chee Hiong CHEW, Erik Nino TOLENTINO, Yusheng LIN, Swee Har KHOR
  • Patent number: 11348878
    Abstract: Implementations of methods of forming a plurality of reinforced die may include forming a plurality of die on a substrate and patterning a metal gang frame to form a plurality of metal plates. The plurality of metal plates may correspond to the plurality of die. The method may include coupling the metal gang frame over the plurality of die and singulating the plurality of die. Each die of the plurality of die may include the corresponding metal plate from the plurality of metal plates coupled over the plurality of die.
    Type: Grant
    Filed: May 28, 2020
    Date of Patent: May 31, 2022
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Erik Nino Tolentino, Chee Hiong Chew, Yusheng Lin, Swee Har Khor
  • Publication number: 20200294935
    Abstract: Implementations of methods of forming a plurality of reinforced die may include forming a plurality of die on a substrate and patterning a metal gang frame to form a plurality of metal plates. The plurality of metal plates may correspond to the plurality of die. The method may include coupling the metal gang frame over the plurality of die and singulating the plurality of die. Each die of the plurality of die may include the corresponding metal plate from the plurality of metal plates coupled over the plurality of die.
    Type: Application
    Filed: May 28, 2020
    Publication date: September 17, 2020
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Erik Nino TOLENTINO, Chee Hiong CHEW, Yusheng LIN, Swee Har KHOR
  • Publication number: 20200286865
    Abstract: Implementations of semiconductor packages may include one or more die coupled over a substrate, an electrically conductive spacer coupled over the substrate, and a clip coupled over and to the one or more die and the electrically conductive spacer. The clip may electrically couple the one or more die and the electrically conductive spacer.
    Type: Application
    Filed: January 17, 2020
    Publication date: September 10, 2020
    Inventors: Chee Hiong CHEW, Erik Nino TOLENTINO, Vemmond Jeng Hung NG, Shutesh KRISHNAN
  • Patent number: 10700018
    Abstract: Implementations of methods of forming a plurality of reinforced die may include forming a plurality of die on a substrate and patterning a metal gang frame to form a plurality of metal plates. The plurality of metal plates may correspond to the plurality of die. The method may include coupling the metal gang frame over the plurality of die and singulating the plurality of die. Each die of the plurality of die may include the corresponding metal plate from the plurality of metal plates coupled over the plurality of die.
    Type: Grant
    Filed: November 6, 2018
    Date of Patent: June 30, 2020
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Erik Nino Tolentino, Chee Hiong Chew, Yusheng Lin, Swee Har Khor
  • Publication number: 20200161209
    Abstract: A power semiconductor package includes a first direct bonded copper (DBC) substrate having a plurality of connection traces on a first face of the first DBC substrate. A plurality of die are coupled to the connection traces, each die coupled to one of the connection traces at a first face of the die. A second DBC substrate includes connection traces on a first face of the second DBC substrate. A second face of each die is coupled to one of the connection traces of the first face of the second DBC substrate. A cavity between the first face of the first DBC substrate and the first face of the second DBC substrate is filled with an encapsulating compound. Terminal pins may be coupled to connection traces on the first face of the first DBC substrate. More than two DBC substrates may be stacked to form a stacked power semiconductor package.
    Type: Application
    Filed: January 27, 2020
    Publication date: May 21, 2020
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Erik Nino TOLENTINO, Vemal Raja MANIKAM, Azhar ARIPIN
  • Publication number: 20200144200
    Abstract: Implementations of methods of forming a plurality of reinforced die may include forming a plurality of die on a substrate and patterning a metal gang frame to form a plurality of metal plates. The plurality of metal plates may correspond to the plurality of die. The method may include coupling the metal gang frame over the plurality of die and singulating the plurality of die. Each die of the plurality of die may include the corresponding metal plate from the plurality of metal plates coupled over the plurality of die.
    Type: Application
    Filed: November 6, 2018
    Publication date: May 7, 2020
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Erik Nino TOLENTINO, Chee Hiong CHEW, Yusheng LIN, Swee Har KHOR
  • Patent number: 10546798
    Abstract: A power semiconductor package includes a first direct bonded copper (DBC) substrate having a plurality of connection traces on a first face of the first DBC substrate. A plurality of die are coupled to the connection traces, each die coupled to one of the connection traces at a first face of the die. A second DBC substrate includes connection traces on a first face of the second DBC substrate. A second face of each die is coupled to one of the connection traces of the first face of the second DBC substrate. A cavity between the first face of the first DBC substrate and the first face of the second DBC substrate is filled with an encapsulating compound. Terminal pins may be coupled to connection traces on the first face of the first DBC substrate. More than two DBC substrates may be stacked to form a stacked power semiconductor package.
    Type: Grant
    Filed: May 8, 2018
    Date of Patent: January 28, 2020
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Erik Nino Tolentino, Vernal Raja Manikam, Azhar Aripin
  • Publication number: 20180261525
    Abstract: A power semiconductor package includes a first direct bonded copper (DBC) substrate having a plurality of connection traces on a first face of the first DBC substrate. A plurality of die are coupled to the connection traces, each die coupled to one of the connection traces at a first face of the die. A second DBC substrate includes connection traces on a first face of the second DBC substrate. A second face of each die is coupled to one of the connection traces of the first face of the second DBC substrate. A cavity between the first face of the first DBC substrate and the first face of the second DBC substrate is filled with an encapsulating compound. Terminal pins may be coupled to connection traces on the first face of the first DBC substrate. More than two DBC substrates may be stacked to form a stacked power semiconductor package.
    Type: Application
    Filed: May 8, 2018
    Publication date: September 13, 2018
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Erik Nino TOLENTINO, Vemal Raja MANIKAM, Azhar ARIPIN
  • Patent number: 9991185
    Abstract: A power semiconductor package includes a first direct bonded copper (DBC) substrate having a plurality of connection traces on a first face of the first DBC substrate. A plurality of die are coupled to the connection traces, each die coupled to one of the connection traces at a first face of the die. A second DBC substrate includes connection traces on a first face of the second DBC substrate. A second face of each die is coupled to one of the connection traces of the first face of the second DBC substrate. A cavity between the first face of the first DBC substrate and the first face of the second DBC substrate is filled with an encapsulating compound. Terminal pins may be coupled to connection traces on the first face of the first DBC substrate. More than two DBC substrates may be stacked to form a stacked power semiconductor package.
    Type: Grant
    Filed: April 18, 2017
    Date of Patent: June 5, 2018
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Erik Nino Tolentino, Vemal Raja Manikam, Azhair Aripin
  • Publication number: 20170221792
    Abstract: A power semiconductor package includes a first direct bonded copper (DBC) substrate having a plurality of connection traces on a first face of the first DBC substrate. A plurality of die are coupled to the connection traces, each die coupled to one of the connection traces at a first face of the die. A second DBC substrate includes connection traces on a first face of the second DBC substrate. A second face of each die is coupled to one of the connection traces of the first face of the second DBC substrate. A cavity between the first face of the first DBC substrate and the first face of the second DBC substrate is filled with an encapsulating compound. Terminal pins may be coupled to connection traces on the first face of the first DBC substrate. More than two DBC substrates may be stacked to form a stacked power semiconductor package.
    Type: Application
    Filed: April 18, 2017
    Publication date: August 3, 2017
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Erik Nino TOLENTINO, Vemal Raja MANIKAM, Azhair ARIPIN
  • Patent number: 9659837
    Abstract: A power semiconductor package includes a first direct bonded copper (DBC) substrate having a plurality of connection traces on a first face of the first DBC substrate. A plurality of die are coupled to the connection traces, each die coupled to one of the connection traces at a first face of the die. A second DBC substrate includes connection traces on a first face of the second DBC substrate. A second face of each die is coupled to one of the connection traces of the first face of the second DBC substrate. A cavity between the first face of the first DBC substrate and the first face of the second DBC substrate is filled with an encapsulating compound. Terminal pins may be coupled to connection traces on the first face of the first DBC substrate. More than two DBC substrates may be stacked to form a stacked power semiconductor package.
    Type: Grant
    Filed: January 30, 2015
    Date of Patent: May 23, 2017
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Erik Nino Tolentino, Vemal Raja Manikam, Azhar Aripin
  • Publication number: 20160225693
    Abstract: A power semiconductor package includes a first direct bonded copper (DBC) substrate having a plurality of connection traces on a first face of the first DBC substrate. A plurality of die are coupled to the connection traces, each die coupled to one of the connection traces at a first face of the die. A second DBC substrate includes connection traces on a first face of the second DBC substrate. A second face of each die is coupled to one of the connection traces of the first face of the second DBC substrate. A cavity between the first face of the first DBC substrate and the first face of the second DBC substrate is filled with an encapsulating compound. Terminal pins may be coupled to connection traces on the first face of the first DBC substrate. More than two DBC substrates may be stacked to form a stacked power semiconductor package.
    Type: Application
    Filed: January 30, 2015
    Publication date: August 4, 2016
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Erik Nino Tolentino, Vemal Raja Manikam, Azhar Aripin