Patents by Inventor Ertugrul Demircan
Ertugrul Demircan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9934349Abstract: A method for design rule verification is provided. The method comprises: providing a design rule check (DRC) deck based on a design rule manual (DRM) having a plurality of design rules; providing a plurality of primitive objects; creating a plurality of collection objects, each collection object using one or more primitive objects; using the plurality of collection objects, creating a plurality of DRM test cases; assigning names to each of the plurality of DRM test cases, each of the names based on a rule name of the plurality of design rules and on an expected pass or fail indication; and using the plurality of named DRM test cases to verify the DRC deck.Type: GrantFiled: March 26, 2015Date of Patent: April 3, 2018Assignee: NXP USA, INC.Inventors: Inder Mohan Bhawnani, Ertugrul Demircan, Dwarka Prasad, Douglas M. Reber, Donald E. Smeltzer, Kenneth J. Danti
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Patent number: 9652577Abstract: This disclosure describes an approach to create a library of pre-marked circuit element objects and use the pre-marked circuit element object library to design and fabricate an integrated circuit. Each of the circuit element objects are “pre-marked” and include embedded voltage markers having independent pre-assigned voltage values for each terminal in the circuit element object. When a circuit designer inserts a pre-marked circuit element object in a schematic design, the design tool determines whether each of the circuit element object terminal's pre-assigned voltage values match their corresponding nets to which they are connected. When the circuit designer completes the schematic design that includes valid nets throughout the schematic design, the design tool generates a layout design from the schematic design. The design tool, in turn, generates mask layer data from the layout design when the layout design passes verification testing.Type: GrantFiled: October 2, 2014Date of Patent: May 16, 2017Assignee: NXP USA, Inc.Inventors: Edward O. Travis, Ertugrul Demircan, Douglas M. Reber, Michael A. Stockinger
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Publication number: 20160283642Abstract: A method for design rule verification is provided. The method comprises: providing a design rule check (DRC) deck based on a design rule manual (DRM) having a plurality of design rules; providing a plurality of primitive objects; creating a plurality of collection objects, each collection object using one or more primitive objects; using the plurality of collection objects, creating a plurality of DRM test cases; assigning names to each of the plurality of DRM test cases, each of the names based on a rule name of the plurality of design rules and on an expected pass or fail indication; and using the plurality of named DRM test cases to verify the DRC deck.Type: ApplicationFiled: March 26, 2015Publication date: September 29, 2016Inventors: INDER MOHAN BHAWNANI, ERTUGRUL DEMIRCAN, DWARKA PRASAD, DOUGLAS M. REBER, DONALD E. SMELTZER, KENNETH J. DANTI
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Publication number: 20160098510Abstract: This disclosure describes an approach to create a library of pre-marked circuit element objects and use the pre-marked circuit element object library to design and fabricate an integrated circuit. Each of the circuit element objects are “pre-marked” and include embedded voltage markers having independent pre-assigned voltage values for each terminal in the circuit element object. When a circuit designer inserts a pre-marked circuit element object in a schematic design, the design tool determines whether each of the circuit element object terminal's pre-assigned voltage values match their corresponding nets to which they are connected. When the circuit designer completes the schematic design that includes valid nets throughout the schematic design, the design tool generates a layout design from the schematic design. The design tool, in turn, generates mask layer data from the layout design when the layout design passes verification testing.Type: ApplicationFiled: October 2, 2014Publication date: April 7, 2016Inventors: Edward O. Travis, Ertugrul Demircan, Douglas M. Reber, Michael A. Stockinger
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Patent number: 9245086Abstract: A technique for electromigration stress mitigation in interconnects of an integrated circuit design includes generating a maximal spanning tree of a directed graph, which represents an interconnect network of an integrated circuit design. A first point on the spanning tree having a lowest stress and a second point on the spanning tree having a highest stress are located. A maximum first stress between the first and second points is determined. In response to determining the maximum first stress between the first and second points is greater than a critical stress, a stub is added to the spanning tree at a node between the first and second points. The maximum first stress between the first and second points is re-determined subsequent to adding the stub.Type: GrantFiled: April 30, 2014Date of Patent: January 26, 2016Assignee: FREESCALE SEMICONDUCTOR, INC.Inventors: Ertugrul Demircan, Mehul D. Shroff
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Patent number: 9219107Abstract: A semiconductor device structure a semiconductor substrate having a first conductivity type and a top surface. A plurality of first doped regions is at a first depth below the top surface arranged in a checkerboard fashion. The first doped regions are of a second conductivity type. A dielectric layer is over the top surface. An inductive element is over the dielectric layer, wherein the inductive element is over the first doped regions.Type: GrantFiled: May 27, 2014Date of Patent: December 22, 2015Assignee: FREESCALE SEMICONDUCTOR, INC.Inventors: Ertugrul Demircan, Thomas F. McNelly
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Publication number: 20150178438Abstract: A first circuit design is entered in an electronic design automation (EDA) computer system. The first circuit design includes a first feature with a first node. A marker is associated with the first node and represents a voltage associated with the first node as an algebraic expression of a numerical value representing a property of the circuit design. The marker is used to determine if the component of the circuit design violates a design rule.Type: ApplicationFiled: December 20, 2013Publication date: June 25, 2015Inventors: ERTUGRUL DEMIRCAN, Douglas M. Reber, Michael A. Stockinger, Edward O. Travis
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Patent number: 9026970Abstract: An approach is provided to generate a number of virtualized circuit designs by applying design-for-manufacturing (DFM) processes to a circuit design. The virtualized circuit designs are checked using design rule checks (DRCs), with the checking resulting in a design rule error quantity that corresponds to each of the virtualized circuit designs. One of the virtualized circuit designs is selected for use in manufacturing the circuit design with the selection based each of the design's design rule error quantities.Type: GrantFiled: March 7, 2013Date of Patent: May 5, 2015Assignee: Freescale Semiconductor, Inc.Inventors: Kenneth J. Danti, Ertugrul Demircan
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Publication number: 20150046893Abstract: A technique for electromigration stress mitigation in interconnects of an integrated circuit design includes generating a maximal spanning tree of a directed graph, which represents an interconnect network of an integrated circuit design. A first point on the spanning tree having a lowest stress and a second point on the spanning tree having a highest stress are located. A maximum first stress between the first and second points is determined. In response to determining the maximum first stress between the first and second points is greater than a critical stress, a stub is added to the spanning tree at a node between the first and second points. The maximum first stress between the first and second points is re-determined subsequent to adding the stub.Type: ApplicationFiled: April 30, 2014Publication date: February 12, 2015Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: ERTUGRUL DEMIRCAN, MEHUL D. SCHROFF
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Publication number: 20140273391Abstract: A semiconductor device structure a semiconductor substrate having a first conductivity type and a top surface. A plurality of first doped regions is at a first depth below the top surface arranged in a checkerboard fashion. The first doped regions are of a second conductivity type. A dielectric layer is over the top surface. An inductive element is over the dielectric layer, wherein the inductive element is over the first doped regions.Type: ApplicationFiled: May 27, 2014Publication date: September 18, 2014Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: Ertugrul Demircan, Thomas F. McNelly
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Publication number: 20140258951Abstract: An approach is provided to generate a number of virtualized circuit designs by applying design-for-manufacturing (DFM) processes to a circuit design. The virtualized circuit designs are checked using design rule checks (DRCs), with the checking resulting in a design rule error quantity that corresponds to each of the virtualized circuit designs. One of the virtualized circuit designs is selected for use in manufacturing the circuit design with the selection based each of the design's design rule error quantities.Type: ApplicationFiled: March 7, 2013Publication date: September 11, 2014Inventors: Kenneth J. Danti, Ertugrul Demircan
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Patent number: 8793632Abstract: In one or more embodiments, one or more methods, processes, and/or systems described can determine stress failures in interconnect segments of integrated circuit designs and correct those failure via modifying the interconnect segments of the integrated circuit designs with one or more additions to the interconnect segments of the integrated circuit designs. Potentials can be received from a simulation, and one or more failures of an interconnect segment can be determined via the potentials from the simulation. For example, a failure can be determined via a comparison with a potential from the simulation and a critical potential. An interconnect segment can be modified with a stub such that a comparison with a potential from the simulation and a critical potential to provide a non-failing, modified interconnect segment.Type: GrantFiled: August 12, 2013Date of Patent: July 29, 2014Assignee: Freescale Semiconductor, Inc.Inventors: Ertugrul Demircan, Mehul D. Shroff
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Patent number: 8766402Abstract: A semiconductor device structure a semiconductor substrate having a first conductivity type and a top surface. A plurality of first doped regions is at a first depth below the top surface arranged in a checkerboard fashion. The first doped regions are of a second conductivity type. A dielectric layer is over the top surface. An inductive element is over the dielectric layer, wherein the inductive element is over the first doped regions.Type: GrantFiled: June 5, 2012Date of Patent: July 1, 2014Assignee: Freescale Semiconductor, Inc.Inventors: Ertugrul Demircan, Thomas F. McNelly
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Patent number: 8713498Abstract: A data processing system determines current information corresponding to a node included at a device design. Physical layout information corresponding to the node is received, the physical layout information including one or more layout geometries, the one or more layout geometries providing a circuit network. The circuit network may be partitioned into two or more network segments. A current conducted at a network segment is identified based on the current information. Information representative of dimensions and metal layer of a layout geometry included at the network segment is received. The computer determines that the current exceeds a predetermined maximum threshold, the predetermined maximum threshold determined based on the dimensions and metal layer.Type: GrantFiled: August 24, 2011Date of Patent: April 29, 2014Assignee: Freescale Semiconductor, Inc.Inventors: Mehul D. Shroff, Ertugrul Demircan
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Publication number: 20130326448Abstract: In one or more embodiments, one or more methods, processes, and/or systems described can determine stress failures in interconnect segments of integrated circuit designs and correct those failure via modifying the interconnect segments of the integrated circuit designs with one or more additions to the interconnect segments of the integrated circuit designs. Potentials can be received from a simulation, and one or more failures of an interconnect segment can be determined via the potentials from the simulation. For example, a failure can be determined via a comparison with a potential from the simulation and a critical potential. An interconnect segment can be modified with a stub such that a comparison with a potential from the simulation and a critical potential to provide a non-failing, modified interconnect segment.Type: ApplicationFiled: August 12, 2013Publication date: December 5, 2013Applicant: Freescale Semiconductor, Inc.Inventors: Ertugrul Demircan, Mehul D. Shroff
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Publication number: 20130320490Abstract: A semiconductor device structure a semiconductor substrate having a first conductivity type and a top surface. A plurality of first doped regions is at a first depth below the top surface arranged in a checkerboard fashion. The first doped regions are of a second conductivity type. A dielectric layer is over the top surface. An inductive element is over the dielectric layer, wherein the inductive element is over the first doped regions.Type: ApplicationFiled: June 5, 2012Publication date: December 5, 2013Inventors: Ertugrul Demircan, Thomas F. McNelly
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Patent number: 8510695Abstract: A technique for determining stress in interconnects of an integrated circuit design includes generating a maximal spanning tree of a directed graph. The directed graph represents an interconnect of an integrated circuit design. The technique also includes locating a first point on the spanning tree that has a lowest stress and a second point on the spanning tree that has a highest stress. The technique further includes determining whether a maximum first stress between the first and second points is less than a critical stress.Type: GrantFiled: May 31, 2012Date of Patent: August 13, 2013Assignee: Freescale Semiconductor, Inc.Inventors: Ertugrul Demircan, Mehul D. Shroff
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Patent number: 8431970Abstract: An integrated circuit has a plurality of terminals for making electrical connection to the integrated circuit. At least one device is formed adjacent an outer edge of the integrated circuit. The device includes at least one metal conductor for forming an edge seal for protecting the integrated circuit during die singulation. The device is coupled to one or more functional circuits within the integrated circuit by routing the at least one metal conductor to the one or more functional circuits, the at least one device providing a reactance value to the one or more functional circuits for non-test operational use. The device may be formed as one or more capacitors or as one or more inductors. Various structures may be used for the capacitor and the inductor.Type: GrantFiled: September 17, 2010Date of Patent: April 30, 2013Assignee: Freescale Semiconductor, Inc.Inventors: Ertugrul Demircan, Jack M. Higman
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Publication number: 20130055184Abstract: A data processing system determines current information corresponding to a node included at a device design. Physical layout information corresponding to the node is received, the physical layout information including one or more layout geometries, the one or more layout geometries providing a circuit network. The circuit network may be partitioned into two or more network segments. A current conducted at a network segment is identified based on the current information. Information representative of dimensions and metal layer of a layout geometry included at the network segment is received. The computer determines that the current exceeds a predetermined maximum threshold, the predetermined maximum threshold determined based on the dimensions and metal layer.Type: ApplicationFiled: August 24, 2011Publication date: February 28, 2013Applicant: Freescale Semiconductor, Inc.Inventors: Mehul D. Shroff, Ertugrul Demircan
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Publication number: 20110001214Abstract: An integrated circuit has a plurality of terminals for making electrical connection to the integrated circuit. At least one device is formed adjacent an outer edge of the integrated circuit. The device includes at least one metal conductor for forming an edge seal for protecting the integrated circuit during die singulation. The device is coupled to one or more functional circuits within the integrated circuit by routing the at least one metal conductor to the one or more functional circuits, the at least one device providing a reactance value to the one or more functional circuits for non-test operational use. The device may be formed as one or more capacitors or as one or more inductors. Various structures may be used for the capacitor and the inductor.Type: ApplicationFiled: September 17, 2010Publication date: January 6, 2011Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: ERTUGRUL DEMIRCAN, JACK M. HIGMAN