Patents by Inventor Erwin Victor Cruz

Erwin Victor Cruz has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10818582
    Abstract: In a general aspect, a method for producing a packaged semiconductor device can include coupling a semiconductor device to a leadframe structure having a signal lead that is electrically coupled with the semiconductor device. The method can also include forming, with a laser, a groove in the signal lead, the groove having a first sidewall and a second sidewall, and applying solder plating to the signal lead, including the first sidewall and the second sidewall of the groove. The method can further include separating, at the groove, the signal lead into a first portion and a second portion, such that the second portion of the signal lead is separated from the metal leadframe structure.
    Type: Grant
    Filed: November 12, 2019
    Date of Patent: October 27, 2020
    Assignee: FAIRCHILD SEMICONDUCTOR CORPORATION
    Inventors: Aira Lourdes Villamor, Erwin Victor Cruz, Geraldine Suico, Silnore Sabando
  • Publication number: 20200083148
    Abstract: In a general aspect, a method for producing a packaged semiconductor device can include coupling a semiconductor device to a leadframe structure having a signal lead that is electrically coupled with the semiconductor device. The method can also include forming, with a laser, a groove in the signal lead, the groove having a first sidewall and a second sidewall, and applying solder plating to the signal lead, including the first sidewall and the second sidewall of the groove.
    Type: Application
    Filed: November 12, 2019
    Publication date: March 12, 2020
    Applicant: FAIRCHILD SEMICONDUCTOR CORPORATION
    Inventors: Aira Lourdes VILLAMOR, Erwin Victor CRUZ, Geraldine SUICO, Silnore SABANDO
  • Patent number: 10483192
    Abstract: In a general aspect, a method for producing a packaged semiconductor device can include coupling a semiconductor device to a leadframe structure having a signal lead that is electrically coupled with the semiconductor device. The method can also include encapsulating at least a portion of the semiconductor device and at least a portion of the leadframe structure in a molding compound. At least a segment of the signal lead can be exposed outside the molding compound. A surface of the molding compound can define a primary plane of the packaged semiconductor device. The method can further include forming, with a laser, a groove in the segment, applying solder plating to the segment, including the groove, and separating, at the groove, the segment into a first portion and a second portion, such that the second portion of the segment is separated from the leadframe structure.
    Type: Grant
    Filed: May 17, 2018
    Date of Patent: November 19, 2019
    Assignee: FAIRCHILD SEMICONDUCTOR CORPORATION
    Inventors: Aira Lourdes Villamor, Erwin Victor Cruz, Geraldine Suico, Silnore Sabando
  • Publication number: 20180269138
    Abstract: In a general aspect, a method for producing a packaged semiconductor device can include coupling a semiconductor device to a leadframe structure having a signal lead that is electrically coupled with the semiconductor device. The method can also include encapsulating at least a portion of the semiconductor device and at least a portion of the leadframe structure in a molding compound. At least a segment of the signal lead can be exposed outside the molding compound. A surface of the molding compound can define a primary plane of the packaged semiconductor device. The method can further include forming, with a laser, a groove in the segment, applying solder plating to the segment, including the groove, and separating, at the groove, the segment into a first portion and a second portion, such that the second portion of the segment is separated from the leadframe structure.
    Type: Application
    Filed: May 17, 2018
    Publication date: September 20, 2018
    Applicant: FAIRCHILD SEMICONDUCTOR CORPORATION
    Inventors: Aira Lourdes VILLAMOR, Erwin Victor CRUZ, Geraldine SUICO, Silnore SABANDO
  • Patent number: 9978668
    Abstract: In a general aspect, a packaged semiconductor device can include a semiconductor device and a metal leadframe structure having a signal lead that is electrically coupled with the semiconductor device. The device can also include a molding compound encapsulating at least a portion of the metal leadframe structure. At least a portion of the signal lead can be exposed outside the molding compound. The device can further include a solder plating disposed on exposed portions of the metal leadframe structure. In the device, a flank of the signal lead can have a surface area. At first portion of the surface area of the flank can be defined by the solder plating, and a second portion of the surface area of the flank can be defined by exposed metal of the metal leadframe structure. A perimeter of a surface of the exposed metal can have at least one curved edge.
    Type: Grant
    Filed: January 17, 2017
    Date of Patent: May 22, 2018
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Aira Lourdes Villamor, Erwin Victor Cruz, Geraldine Suico, Silnore Sabando
  • Patent number: 8513059
    Abstract: A method for making a premolded clip structure is disclosed. The method includes obtaining a first clip and a second clip, and forming a molding material around the first clip comprising a first surface and the second clip comprising a second surface. The first surface of the first clip structure and the second surface of the second clip structure are exposed through the molding material, and a premolded clip structure is then formed.
    Type: Grant
    Filed: July 19, 2011
    Date of Patent: August 20, 2013
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Erwin Victor Cruz, Maria Cristina B. Estacio
  • Publication number: 20110272794
    Abstract: A method for making a premolded clip structure is disclosed. The method includes obtaining a first clip and a second clip, and forming a molding material around the first clip comprising a first surface and the second clip comprising a second surface. The first surface of the first clip structure and the second surface of the second clip structure are exposed through the molding material, and a premolded clip structure is then formed.
    Type: Application
    Filed: July 19, 2011
    Publication date: November 10, 2011
    Inventors: Erwin Victor Cruz, Maria Cristina B. Estacio
  • Patent number: 8008759
    Abstract: A method for making a premolded clip structure is disclosed. The method includes obtaining a first clip and a second clip, and forming a molding material around the first clip comprising a first surface and the second clip comprising a second surface. The first surface of the first clip structure and the second surface of the second clip structure are exposed through the molding material, and a premolded clip structure is then formed.
    Type: Grant
    Filed: June 24, 2010
    Date of Patent: August 30, 2011
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Erwin Victor Cruz, Maria Cristina B. Estacio
  • Patent number: 7838340
    Abstract: A method for making a premolded clip structure is disclosed. The method includes obtaining a first clip and a second clip, and forming a molding material around the first clip comprising a first surface and the second clip comprising a second surface. The first surface of the first clip structure and the second surface of the second clip structure are exposed through the molding material, and a premolded clip structure is then formed.
    Type: Grant
    Filed: June 24, 2010
    Date of Patent: November 23, 2010
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Erwin Victor Cruz, Maria Cristina B. Estacio
  • Publication number: 20100258923
    Abstract: A method for making a premolded clip structure is disclosed. The method includes obtaining a first clip and a second clip, and forming a molding material around the first clip comprising a first surface and the second clip comprising a second surface. The first surface of the first clip structure and the second surface of the second clip structure are exposed through the molding material, and a premolded clip structure is then formed.
    Type: Application
    Filed: June 24, 2010
    Publication date: October 14, 2010
    Inventors: Erwin Victor Cruz, Maria Cristina B. Estacio
  • Publication number: 20100258924
    Abstract: A method for making a premolded clip structure is disclosed. The method includes obtaining a first clip and a second clip, and forming a molding material around the first clip comprising a first surface and the second clip comprising a second surface. The first surface of the first clip structure and the second surface of the second clip structure are exposed through the molding material, and a premolded clip structure is then formed.
    Type: Application
    Filed: June 24, 2010
    Publication date: October 14, 2010
    Inventors: Erwin Victor Cruz, Maria Cristina B. Estacio
  • Patent number: 7768105
    Abstract: A method for making a premolded clip structure is disclosed. The method includes obtaining a first clip and a second clip, and forming a molding material around the first clip comprising a first surface and the second clip comprising a second surface. The first surface of the first clip structure and the second surface of the second clip structure are exposed through the molding material, and a premolded clip structure is then formed.
    Type: Grant
    Filed: January 24, 2007
    Date of Patent: August 3, 2010
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Erwin Victor Cruz, Maria Cristina B. Estacio
  • Publication number: 20090224383
    Abstract: A clip structure and semiconductor die package. The clip structure includes a first portion and a second portion, with a connecting structure located between the first and second portion. The clip structure is substantially planar. The semiconductor die package includes a semiconductor die located between a leadframe structure and a clip structure. Slots are formed within the molding material covering portions of the semiconductor die package. The slots are located between a first portion and the second portion of the clip structure, and the slot overlap with the semiconductor die.
    Type: Application
    Filed: March 7, 2008
    Publication date: September 10, 2009
    Inventors: Erwin Victor Cruz, Maria Cristina Estacio
  • Publication number: 20090057855
    Abstract: A semiconductor die package. It includes a semiconductor die including a first surface and a second surface opposite the first surface, an optional conductive structure, and a leadframe structure. The leadframe structure comprises a central portion suitable for supporting the semiconductor die, and a plurality of stand-off structures coupled to the central portion of the leadframe structure. The stand-off structures can support the conductive structure, and the conductive structure is attached to the second surface of the semiconductor die.
    Type: Application
    Filed: August 30, 2007
    Publication date: March 5, 2009
    Inventors: Maria Clemens Quinones, Erwin Victor Cruz, Marvin Gestole, Ruben P. Madrid, Connie N. Tangpuz
  • Publication number: 20080173991
    Abstract: A method for making a premolded clip structure is disclosed. The method includes obtaining a first clip and a second clip, and forming a molding material around the first clip comprising a first surface and the second clip comprising a second surface. The first surface of the first clip structure and the second surface of the second clip structure are exposed through the molding material, and a premolded clip structure is then formed.
    Type: Application
    Filed: January 24, 2007
    Publication date: July 24, 2008
    Inventors: Erwin Victor Cruz, Maria Cristina B. Estacio
  • Publication number: 20080044946
    Abstract: A clip structure for a semiconductor package is disclosed. The clip structure includes a major portion, at least one pedestal extending from the major portion, a downset portion, and a lead portion. The downset portion is between the lead portion and the major portion. The clip structure can be used in a MLP (micro-leadframe package).
    Type: Application
    Filed: September 17, 2007
    Publication date: February 21, 2008
    Inventors: Erwin Victor Cruz, Elsie Cabahug, Ti Ching Shian, Venkat Iyer
  • Publication number: 20060189116
    Abstract: A method for forming a stud bumped semiconductor die is disclosed. The method includes forming a ball at the tip of a coated wire passing through a hole in a capillary, where the coated wire has a core and an oxidation-resistant coating. The formed ball is pressed to the conductive region on the semiconductor die. The coated wire is cut, thereby leaving a conductive stud bump on the conductive region, where the conductive stud bump includes an inner conductive portion and an outer oxidation-resistant layer.
    Type: Application
    Filed: April 14, 2006
    Publication date: August 24, 2006
    Inventors: Rajeev Joshi, Consuelo Tangpuz, Margie Rios, Erwin Victor Cruz