Patents by Inventor Erwin Victor R. Cruz

Erwin Victor R. Cruz has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8497164
    Abstract: A semiconductor die package. The semiconductor die package includes a premolded clip structure assembly having a clip structure, a semiconductor die attached to the clip structure, and a first molding material covering at least a portion of the clip structure and the semiconductor die. The semiconductor die package also includes a leadframe structure having a die attach pad, where the leadframe structure is attached to premolded clip structure assembly.
    Type: Grant
    Filed: July 13, 2012
    Date of Patent: July 30, 2013
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Armand Vincent C. Jereza, Paul Armand Calo, Erwin Victor R. Cruz
  • Publication number: 20120329214
    Abstract: A semiconductor die package. The semiconductor die package includes a premolded clip structure assembly having a clip structure, a semiconductor die attached to the clip structure, and a first molding material covering at least a portion of the clip structure and the semiconductor die. The semiconductor die package also includes a leadframe structure having a die attach pad, where the leadframe structure is attached to premolded clip structure assembly.
    Type: Application
    Filed: July 13, 2012
    Publication date: December 27, 2012
    Inventors: Armand Vincent C. Jereza, Paul Armand Calo, Erwin Victor R. Cruz
  • Patent number: 8222718
    Abstract: A semiconductor die package. The semiconductor die package includes a premolded clip structure assembly having a clip structure, a semiconductor die attached to the clip structure, and a first molding material covering at least a portion of the clip structure and the semiconductor die. The semiconductor die package also includes a leadframe structure having a die attach pad, where the leadframe structure is attached to premolded clip structure assembly.
    Type: Grant
    Filed: February 5, 2009
    Date of Patent: July 17, 2012
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Armand Vincent C. Jereza, Paul Armand Calo, Erwin Victor R. Cruz
  • Patent number: 8058107
    Abstract: A clip structure for a semiconductor package is disclosed. The clip structure includes a major portion, at least one pedestal extending from the major portion, a downset portion, and a lead portion. The downset portion is between the lead portion and the major portion. The clip structure can be used in a MLP (micro-leadframe package).
    Type: Grant
    Filed: September 17, 2007
    Date of Patent: November 15, 2011
    Inventors: Erwin Victor R. Cruz, Elsie Cabahug, Ti Ching Shian, Venkat Iyer
  • Patent number: 7972906
    Abstract: A clip structure and semiconductor die package. The clip structure includes a first portion and a second portion, with a connecting structure located between the first and second portion. The clip structure is substantially planar. The semiconductor die package includes a semiconductor die located between a leadframe structure and a clip structure. Slots are formed within the molding material covering portions of the semiconductor die package. The slots are located between a first portion and the second portion of the clip structure, and the slot overlap with the semiconductor die.
    Type: Grant
    Filed: March 7, 2008
    Date of Patent: July 5, 2011
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Erwin Victor R. Cruz, Maria Cristina B. Estacio
  • Patent number: 7932171
    Abstract: A method for forming a stud bumped semiconductor die is disclosed. The method includes forming a ball at the tip of a coated wire passing through a hole in a capillary, where the coated wire has a core and an oxidation-resistant coating. The formed ball is pressed to the conductive region on the semiconductor die. The coated wire is cut, thereby leaving a conductive stud bump on the conductive region, where the conductive stud bump includes an inner conductive portion and an outer oxidation-resistant layer.
    Type: Grant
    Filed: January 22, 2009
    Date of Patent: April 26, 2011
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Rajeev Joshi, Consuelo Tangpuz, Margie T. Rios, Erwin Victor R. Cruz
  • Publication number: 20100193921
    Abstract: A semiconductor die package. The semiconductor die package includes a premolded clip structure assembly having a clip structure, a semiconductor die attached to the clip structure, and a first molding material covering at least a portion of the clip structure and the semiconductor die. The semiconductor die package also includes a leadframe structure having a die attach pad, where the leadframe structure is attached to premolded clip structure assembly.
    Type: Application
    Filed: February 5, 2009
    Publication date: August 5, 2010
    Inventors: Armand Vincent C. Jereza, Paul Armand Calo, Erwin Victor R. Cruz
  • Publication number: 20090186452
    Abstract: A method for forming a stud bumped semiconductor die is disclosed. The method includes forming a ball at the tip of a coated wire passing through a hole in a capillary, where the coated wire has a core and an oxidation-resistant coating. The formed ball is pressed to the conductive region on the semiconductor die. The coated wire is cut, thereby leaving a conductive stud bump on the conductive region, where the conductive stud bump includes an inner conductive portion and an outer oxidation-resistant layer.
    Type: Application
    Filed: January 22, 2009
    Publication date: July 23, 2009
    Inventors: Rajeev Joshi, Consuelo Tangpuz, Margie T. Rios, Erwin Victor R. Cruz
  • Patent number: 7501337
    Abstract: A method for forming a stud bumped semiconductor die is disclosed. The method includes forming a ball at the tip of a coated wire passing through a hole in a capillary, where the coated wire has a core and an oxidation-resistant coating. The formed ball is pressed to the conductive region on the semiconductor die. The coated wire is cut, thereby leaving a conductive stud bump on the conductive region, where the conductive stud bump includes an inner conductive portion and an outer oxidation-resistant layer.
    Type: Grant
    Filed: April 14, 2006
    Date of Patent: March 10, 2009
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Rajeev Joshi, Consuelo Tangpuz, Margie T. Rios, Erwin Victor R. Cruz
  • Patent number: 7402462
    Abstract: A folded frame carrier has a die attach pad (DAP) 30 and one or more folded edges 32, 33, 34, 35. Each folded edge has one or more studs 36 and each stud has a trapezoidal tip. The folded frame carrier may be made of single gauge copper or copper alloy. Multiple folded frame carriers may be formed between opposite rails of a lead frame. The folded edges are cut with a relief groove. The tips are formed in edges of the DAP and then the tips are folded upright. The tips provide electrical connection to the terminal on the rear surface of a power semiconductor mounted on the DAP.
    Type: Grant
    Filed: July 12, 2005
    Date of Patent: July 22, 2008
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Ruben P. Madrid, Marvin Gestole, Erwin Victor R. Cruz, Romel N. Madatad, Arniel Jaud, Paul Armand Calo
  • Patent number: 7285849
    Abstract: A clip structure for a semiconductor package is disclosed. The clip structure includes a major portion, at least one pedestal extending from the major portion, a downset portion, and a lead portion. The downset portion is between the lead portion and the major portion. The clip structure can be used in a MLP (micro-leadframe package).
    Type: Grant
    Filed: November 18, 2005
    Date of Patent: October 23, 2007
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Erwin Victor R. Cruz, Elsie Cabahug, Ti Ching Shian, Venkat Iyer
  • Patent number: 7271497
    Abstract: A method for forming a stud bumped semiconductor die is disclosed. The method includes forming a ball at the tip of a coated wire passing through a hole in a capillary, where the coated wire has a core and an oxidation-resistant coating. The formed ball is pressed to the conductive region on the semiconductor die. The coated wire is cut, thereby leaving a conductive stud bump on the conductive region, where the conductive stud bump includes an inner conductive portion and an outer oxidation-resistant layer.
    Type: Grant
    Filed: March 10, 2003
    Date of Patent: September 18, 2007
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Rajeev Joshi, Consuelo Tangpuz, Margie T. Rios, Erwin Victor R. Cruz
  • Publication number: 20070114352
    Abstract: A clip structure for a semiconductor package is disclosed. The clip structure includes a major portion, at least one pedestal extending from the major portion, a downset portion, and a lead portion. The downset portion is between the lead portion and the major portion. The clip structure can be used in a MLP (micro-leadframe package).
    Type: Application
    Filed: November 18, 2005
    Publication date: May 24, 2007
    Inventors: Erwin Victor R. Cruz, Elsie Cabahug, Ti Ching Shian, Venkat Iyer
  • Patent number: 6943434
    Abstract: A packaging assembly for semiconductor devices and a method for making such packaging is described. The invention provides a non-Pb bump design during a new flip-chip method of packaging. The design uses special conductive materials in a stud form, rather than a solder ball containing Pb. This configuration maintains a desirable solder thickness between the die and the leadframe and forms a high standoff by restricting solder wettabilty on the leadframe side. This configuration also absorbs any stress and protects the die from cracking. The invention also provides methods for making such semiconductor packages.
    Type: Grant
    Filed: October 2, 2003
    Date of Patent: September 13, 2005
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Consuelo N. Tangpuz, Romel N. Manatad, Margie T. Rios, Erwin Victor R. Cruz
  • Publication number: 20040178481
    Abstract: A method for forming a stud bumped semiconductor die is disclosed. The method includes forming a ball at the tip of a coated wire passing through a hole in a capillary, where the coated wire has a core and an oxidation-resistant coating. The formed ball is pressed to the conductive region on the semiconductor die. The coated wire is cut, thereby leaving a conductive stud bump on the conductive region, where the conductive stud bump includes an inner conductive portion and an outer oxidation-resistant layer.
    Type: Application
    Filed: March 10, 2003
    Publication date: September 16, 2004
    Inventors: Rajeev Joshi, Consuelo Tangpuz, Margie T. Rios, Erwin Victor R. Cruz
  • Publication number: 20040130009
    Abstract: A packaging assembly for semiconductor devices and a method for making such packaging is described. The invention provides a non-Pb bump design during a new flip-chip method of packaging. The design uses special conductive materials in a stud form, rather than a solder ball containing Pb. This configuration maintains a desirable solder thickness between the die and the leadframe and forms a high standoff by restricting solder wettabilty on the leadframe side. This configuration also absorbs any stress and protects the die from cracking. The invention also provides methods for making such semiconductor packages.
    Type: Application
    Filed: October 2, 2003
    Publication date: July 8, 2004
    Inventors: Consuelo N. Tangpuz, Romel N. Manatad, Margie T. Rios, Erwin Victor R. Cruz
  • Patent number: 6731003
    Abstract: A method for forming a semiconductor die package is disclosed. In one embodiment, the method includes forming a semiconductor die comprising a semiconductor device. A plurality of copper bumps is formed on the semiconductor die using a plating process. An adhesion layer is formed on each of the copper bumps, and a noble metal layer is formed on each of the copper bumps.
    Type: Grant
    Filed: March 11, 2003
    Date of Patent: May 4, 2004
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Rajeev Joshi, Consuelo Tangpuz, Erwin Victor R. Cruz
  • Publication number: 20030173684
    Abstract: A method for forming a semiconductor die package is disclosed. In one embodiment, the method includes forming a semiconductor die comprising a semiconductor device. A plurality of copper bumps is formed on the semiconductor die using a plating process. An adhesion layer is formed on each of the copper bumps, and a noble metal layer is formed on each of the copper bumps.
    Type: Application
    Filed: March 11, 2003
    Publication date: September 18, 2003
    Inventors: Rajeev Joshi, Consuelo Tangpuz, Erwin Victor R. Cruz