Patents by Inventor Eugen Igor Muehldorf

Eugen Igor Muehldorf has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4074851
    Abstract: Level sensitive testing is performed on a generalized and modular logic with embedded array system that is utilized as an arithmetic/logical unit in a digital computer. Each arithmetic/logical unit of a computer is formed of arrangements of combinational logic networks, arrays and storage circuitry. The storage circuitry has the capability for performing scan-in/scan-out operations independently of the system input/output and controls. Using the scan capability, the method of the invention provides for the state of the storage circuitry to be preconditioned and independent of its prior history. Test patterns from an automatic test generator are cycled through the networks of combinational logic and arrays and their respective associated storage circuitry for removal through the scan arrangement to determine their fault status.
    Type: Grant
    Filed: June 30, 1976
    Date of Patent: February 21, 1978
    Assignee: International Business Machines Corporation
    Inventors: Edward Baxter Eichelberger, Eugen Igor Muehldorf, Ronald Gene Walther, Thomas Walter Williams
  • Patent number: 3987286
    Abstract: A standard logic array can be electrically altered at different time intervals to execute complex logic functions. Input variables to the array are processed in a network to generate sets of implicants of a complex function in one or more time periods. The implicants constituting the function are processed through a logic network or matrix as the logic personality of the matrix is altered. The implicant and logic networks may be personalized by (a) structure, (b) time signals, (c) personality signals, and (d) any combination of (a), (b) and (c). The standard array executes complex functions in a single time period or by processing one or more implicants in groups at different time periods. The testability of the array may be improved by appropriate interconnections of the array elements. The invention reduces the number of logic elements or part numbers a system designer must assemble to achieve desired objectives for a data processing machine.
    Type: Grant
    Filed: December 20, 1974
    Date of Patent: October 19, 1976
    Assignee: International Business Machines Corporation
    Inventor: Eugen Igor Muehldorf