Abstract: A die probe including a probe tip operably connected to a first surface of a thin film; a metal trace, wherein a first portion of the metal trace is operably connected to a second surface of the thin film, the second surface of the thin film opposite the first surface of the thin film; and an upper space transformer, wherein a second portion of the metal trace is operably connected to the upper space transformer, wherein a pressurized liquid and/or gas is configured to expand a space between the second surface of the thin film and the upper space transformer.

Abstract: A die probe including a probe tip operably connected to a first surface of a thin film; a metal trace, wherein a first portion of the metal trace is operably connected to a second surface of the thin film, the second surface of the thin film opposite the first surface of the thin film; and an upper space transformer, wherein a second portion of the metal trace is operably connected to the upper space transformer, wherein a pressurized liquid and/or gas is configured to expand a space between the second surface of the thin film and the upper space transformer.

Abstract: Technical solutions are described for optimizing a set of test configurations used for testing an electronic circuit that includes latches. An example method includes receiving a test configuration that includes settings that initiate a set of predetermined input values and corresponding expected output values. The method also includes evaluating the test configuration by executing the electronic circuit according to the test configuration and recording parametric data during the execution, where the parametric data is representative of switching activity of the latches in the electronic circuit. The evaluation includes analyzing the parametric data to identify presence of a predetermined pattern in the switching activity and selecting the test configuration based on the predetermined pattern being absent/present in the switching activity.

Abstract: Testing a Decision Feedback Equalizer (‘DFE’), the DFE including a summing amplifier operatively coupled to a plurality of latches and an input signal line for receiving a data signal, including: preventing a differential data signal from being received by the summing amplifier; and iteratively for each tap to be tested: setting a tap coefficient for each tap to zero; setting an output of the plurality of latches to a predetermined value; setting a tap coefficient for the tap to be tested to a full scale value; and determining whether a resultant output signal from the DFE matches a predetermined expected output signal.

Abstract: Testing a digital-to-analog converter (DAC), where the test is carried out iteratively for a plurality of digital test signal values, includes: providing the digital test signal to a DAC under test and to a servo; providing, by the DAC under test to a summer, an analog test signal, including converting the digital test signal to the analog test signal; providing, by the summer to an observation latch, a summed signal, including summing the analog test signal and an analog offset signal, the analog offset signal received from a second DAC; providing, by the observation latch to the servo, a sample of the summed signal; providing, by the servo to the second DAC in dependence upon the sample and the digital test signal, a digital offset signal, where the second DAC converts the digital offset signal to the analog offset signal; and storing, as a digital observation, the digital offset signal.

Abstract: Testing a digital-to-analog converter (DAC), where the test is carried out iteratively for a plurality of digital test signal values, includes: providing the digital test signal to a DAC under test and to a servo; providing, by the DAC under test to a summer, an analog test signal, including converting the digital test signal to the analog test signal; providing, by the summer to an observation latch, a summed signal, including summing the analog test signal and an analog offset signal, the analog offset signal received from a second DAC; providing, by the observation latch to the servo, a sample of the summed signal; providing, by the servo to the second DAC in dependence upon the sample and the digital test signal, a digital offset signal, where the second DAC converts the digital offset signal to the analog offset signal; and storing, as a digital observation, the digital offset signal.

Abstract: Testing a Decision Feedback Equalizer (‘DFE’), the DFE including a summing amplifier operatively coupled to a plurality of latches and an input signal line for receiving a data signal, including: preventing a differential data signal from being received by the summing amplifier; and iteratively for each tap to be tested: setting a tap coefficient for each tap to zero; setting an output of the plurality of latches to a predetermined value; setting a tap coefficient for the tap to be tested to a full scale value; and determining whether a resultant output signal from the DFE matches a predetermined expected output signal.

Abstract: Testing a Decision Feedback Equalizer (‘DFE’), the DFE including a summing amplifier operatively coupled to a plurality of latches and an input signal line for receiving a data signal, including: preventing a differential data signal from being received by the summing amplifier; and iteratively for each tap to be tested: setting a tap coefficient for each tap to zero; setting an output of the plurality of latches to a predetermined value; setting a tap coefficient for the tap to be tested to a full scale value; and determining whether a resultant output signal from the DFE matches a predetermined expected output signal.

Abstract: Testing a Decision Feedback Equalizer (‘DFE’), the DFE including a summing amplifier operatively coupled to a plurality of latches and an input signal line for receiving a data signal, including: preventing a differential data signal from being received by the summing amplifier; and iteratively for each tap to be tested: setting a tap coefficient for each tap to zero; setting an output of the plurality of latches to a predetermined value; setting a tap coefficient for the tap to be tested to a full scale value; and determining whether a resultant output signal from the DFE matches a predetermined expected output signal.

Abstract: Solder compositions are introduced to interface between an IC chip and its associated heat exchanger cover. The solder compositions have a solidus-liquidus temperature range that encompasses the IC chip operational temperature range. The solder composition has the desired property of absorbing and rejecting heat energy by changing state or phase with each temperature rise and decline that result from temperature fluctuations associated with the thermal cycles of the integrated circuit chips. The electronic module cover is a cap with a heat exchanger formed or attached as a single construction, and made of the same material as the substrate, or made with materials of compatible thermal coefficients of expansion to mitigate the effects of vertical displacement during thermal cycling.

Abstract: Solder compositions are introduced to interface between an IC chip and its associated heat exchanger cover. The solder compositions have a solidus-liquidus temperature range that encompasses the IC chip operational temperature range. The solder composition has the desired property of absorbing and rejecting heat energy by changing state or phase with each temperature rise and decline that result from temperature fluctuations associated with the thermal cycles of the integrated circuit chips.

Abstract: Solder compositions are introduced to interface between an IC chip and its associated heat exchanger cover. The solder compositions have a solidus-liquidus temperature range that encompasses the IC chip operational temperature range. The solder composition has the desired property of absorbing and rejecting heat energy by changing state or phase with each temperature rise and decline that result from temperature fluctuations associated with the thermal cycles of the integrated circuit chips. A path for high thermal conduction (low thermal resistance) from the IC chip to the heat exchanger to the ambient air is provided by an electronic module cover, configured as a cap with a heat exchanger formed or attached as a single construction, and made of the same material as the substrate, or made with materials of compatible thermal coefficients of expansion to mitigate the effects of vertical displacement during thermal cycling.

Abstract: A heat sink in a heat transfer relationship with a substrate such as an integrated chip, chip carrier, or other electronic package. The heat sink is connected to a frame which is connected to a printed circuit board or other suitable support on which the substrate is positioned. The heat sink, which extends through an aperture in the frame is coupled to a surface of the substrate. The heat sink is mechanically decoupled from the substrate. Large heat sinks may be thermally connected to surface mount substrates mounted using technologies such as ceramic ball or column grid arrays, plastic ball or column grid arrays, or solder balls or columns. The heat sink is attached coaxially through the aperture to the substrate. After assembly and lead/tin or other metallic surface mount interconnects are relaxed such that the substrate and is completely supported by the frame and the heat sink imparts zero or nearly zero downward force.

Abstract: A wafer test and burn-in fixture and methodology including a wafer probe having flexible tabs and a load board coupled to the wafer probe using the flexible tabs. The fixture also includes a bladder which biases the wafer probe to contact a wafer. A temperature control apparatus is provided to control the temperature of the wafer probe and the wafer. Tests are performed on the wafer using built-in self tests or wrap wiring tests.

Abstract: A microelectronic module comprising at least two chips mounted to a chip receiving surface. Each chip having an edge including at least one chip input and one chip output. The chips are arranged such that the edge of one chip is opposite the edge of the other chip. The chips are spaced apart by a predetermined distance. Each chip includes at least one optical transmitter attached to the edge of the chip. The transmitter has an input coupled to the chip output and a transmission portion for generating optical signals at a predetermined angle and that are representative of signals inputted to the transmitter input. The microelectronic module further includes at least one optical receiver attached to the edge of the chip. The optical receiver has an output coupled to the chip input and a receiving portion for directly receiving optical signals generated by a corresponding optical transmitter of the other chip. The optical receiver and the corresponding optical transmitter form a transmitter/receiver pair.

Abstract: A heat sink is placed in a heat transfer relationship with a substrate such as an integrated chip, chip carrier, or other electronic package, without imparting stressful forces to the substrate by connecting the heat sink to a frame which is connected to a support such as a printed circuit board or other suitable carrier on which the substrate is positioned. The heat sink extends through an aperture in the frame and is in heat transfer relationship with a surface of the substrate; however, it is mechanically decoupled from the substrate. The invention has particular application in thermally connecting large heat sinks to substrates that are surface mounted on the support using technologies such as ceramic ball or column grid arrays, plastic ball or column grid arrays, or solder balls or columns.

Abstract: A chip package includes a substrate formed from a first die and its attendant wiring interconnections, having a first thermal coefficient of expansion. The first die includes primary input/output (I/O) interconnections for the chip package. Also provided is a second die that includes escape wiring formed on that die and coupled to the primary I/O interconnections through the first die. The second die has a second thermal coefficient of expansion similar to the first thermal coefficient of expansion. The chip package also includes connectors that couple the primary I/O interconnections of the first die to a second level package. An interposer may be provided to couple the primary I/O interconnections to the second level package. The second die is smaller than the first die. The peripheral area of the first die is left exposed when the second die is coupled to the first die so that sufficient I/O interconnections may be formed for the primary I/O interconnections on the first die.