Patents by Inventor Eugene Saghi

Eugene Saghi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180113639
    Abstract: A system and method for efficient variable length memory frame allocation are described. The method is described to include receiving a frame allocation request from a host system, allocating a super frame from a stack of free super frames for the frame allocation request, the super frame comprising a set of consecutively numbered frames, updating entries in a super frame bitmap to indicate that the super frame has been allocated from the stack of free super frames, determining a super frame identifier for the allocated super frame, and enabling the super frame or the set of consecutively numbered frames to be allocated to storing data in connection with the frame allocation request or subsequent frame allocation requests from the host system.
    Type: Application
    Filed: October 26, 2016
    Publication date: April 26, 2018
    Inventors: Horia Simionescu, Eugene Saghi, Sridhar Rao Veerla, Panthini Pandit, Timothy Hoglund, Gowrisankar Radhakrishnan
  • Patent number: 9792245
    Abstract: Embodiments herein provide for efficient memory mapping in a PCIe device when a host changes memory allocations in the device. One PCIe device comprises a plurality of Base Address Registers (BARs) defined by the host. The device also includes a processor with an address space. The processor maps addresses of the address space to the BARs for routing PCIe packets from the host. The processor can determine that the host is reconfiguring the BARs, and, based on the determination, mark packets existing in the computer memory as old, change the BARs in the computer memory as directed by the host, mark packets received after the BAR change as new, process the old packets from the computer memory based on their addresses of the address space until a new packet is reached, and to remap the BARs to the addresses of the address space after the new packet is reached.
    Type: Grant
    Filed: December 9, 2014
    Date of Patent: October 17, 2017
    Assignee: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
    Inventors: Ramprasad Raghavan, Eugene Saghi
  • Patent number: 9424224
    Abstract: Systems and methods presented herein provide for tunneling PCIe data through a SAS domain. a data system includes a SAS expander, a PCIe target device coupled to the expander, and a SAS controller communicatively coupled to a host system and the expander. The controller is operable to open a connection with the expander via the SAS protocol, and to transport packet data between the target device and the host system through the connection via the PCIe protocol. For example, the controller and the expander may be operable to buffer packets of data in the connection. The controller may issue a number of the data packets to be transferred in the connection. Then, the issued number of data packets are transported between the target device and the host system through the connection via the PCIe protocol.
    Type: Grant
    Filed: June 27, 2013
    Date of Patent: August 23, 2016
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: William W. Voorhees, George O. Penokie, William K. Petty, Ramprasad Raghavan, Eugene Saghi
  • Patent number: 9424219
    Abstract: A system includes a PCIe controller coupled to a device through a nontransparent PCIe bridge. The controller is operable to direct I/O operations to the device on behalf of a host system. The system also includes a PCIe driver operable within the host system to generate I/O request descriptors that specify movement of data from the PCIe controller to the host system as well as from the host system to the PCIe controller. The PCIe controller processes the I/O request descriptors and determines which device is involved in the specified movement of data. The PCIe controller generates I/O commands that contain routing information for the device (e.g., memory addresses and steering information) to route the data between the memory address of the host system and the memory address of the device, bypassing a memory of the PCIe controller.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: August 23, 2016
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Eugene Saghi, Richard Solomon, Timothy E. Hoglund
  • Publication number: 20160162436
    Abstract: Embodiments herein provide for efficient memory mapping in a PCIe device when a host changes memory allocations in the device. One PCIe device comprises a plurality of Base Address Registers (BARs) defined by the host. The device also includes a processor with an address space. The processor maps addresses of the address space to the BARs for routing PCIe packets from the host. The processor can determine that the host is reconfiguring the BARs, and, based on the determination, mark packets existing in the computer memory as old, change the BARs in the computer memory as directed by the host, mark packets received after the BAR change as new, process the old packets from the computer memory based on their addresses of the address space until a new packet is reached, and to remap the BARs to the addresses of the address space after the new packet is reached.
    Type: Application
    Filed: December 9, 2014
    Publication date: June 9, 2016
    Inventors: Ramprasad Raghavan, Eugene Saghi
  • Patent number: 9009370
    Abstract: A dynamically controllable buffering system includes a data buffer that is communicatively coupled between first and second data interfaces and operable to perform as an elasticity first-in-first-out buffer in a first mode and to perform as a store-and-forward buffer in a second mode. The system also includes a controller that is operable to detect data rates of the first and second data interfaces, to operate the data buffer in the first mode when the first data interface has a data transfer rate that is faster than a data transfer rate of the second data interface, and to operate the data buffer in the second mode when the second data interface has a data transfer rate that is faster than the data transfer rate of the first data interface.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: April 14, 2015
    Assignee: LSI Corporation
    Inventors: Richard Solomon, Eugene Saghi, John C. Udell
  • Publication number: 20150039787
    Abstract: Systems and methods presented herein provide for coupling a storage controller to a plurality of different storage device types. One embodiment of the storage controller includes an interface operable to communicatively couple to a storage device. The storage controller also includes a processor operable to select between hardware protocol detection of the storage device and firmware protocol detection of the storage device, and to detect a protocol of the storage device when the storage device communicatively couples to the interface according to the selected protocol detection. The storage controller then selects a protocol to process input/output requests from a host based on the detected protocol of the storage device.
    Type: Application
    Filed: August 12, 2013
    Publication date: February 5, 2015
    Applicant: LSI CORPORATION
    Inventors: William W. Voorhees, William K. Petty, Eugene Saghi
  • Patent number: 8943234
    Abstract: Systems and methods presented herein provide for coupling a storage controller to a plurality of different storage device types. One embodiment of the storage controller includes an interface operable to communicatively couple to a storage device. The storage controller also includes a processor operable to select between hardware protocol detection of the storage device and firmware protocol detection of the storage device, and to detect a protocol of the storage device when the storage device communicatively couples to the interface according to the selected protocol detection. The storage controller then selects a protocol to process input/output requests from a host based on the detected protocol of the storage device.
    Type: Grant
    Filed: August 12, 2013
    Date of Patent: January 27, 2015
    Assignee: LSI Corporation
    Inventors: William W. Voorhees, William K. Petty, Eugene Saghi
  • Publication number: 20140372637
    Abstract: Systems and methods presented herein provide for tunneling PCIe data through a SAS domain. a data system includes a SAS expander, a PCIe target device coupled to the expander, and a SAS controller communicatively coupled to a host system and the expander. The controller is operable to open a connection with the expander via the SAS protocol, and to transport packet data between the target device and the host system through the connection via the PCIe protocol. For example, the controller and the expander may be operable to buffer packets of data in the connection. The controller may issue a number of the data packets to be transferred in the connection. Then, the issued number of data packets are transported between the target device and the host system through the connection via the PCIe protocol.
    Type: Application
    Filed: June 27, 2013
    Publication date: December 18, 2014
    Inventors: William W. Voorhees, George O. Penokie, William K. Petty, Ramprasad Raghavan, Eugene Saghi
  • Publication number: 20140281106
    Abstract: A system includes a PCIe controller coupled to a device through a nontransparent PCIe bridge. The controller is operable to direct I/O operations to the device on behalf of a host system. The system also includes a PCIe driver operable within the host system to generate I/O request descriptors that specify movement of data from the PCIe controller to the host system as well as from the host system to the PCIe controller. The PCIe controller processes the I/O request descriptors and determines which device is involved in the specified movement of data. The PCIe controller generates I/O commands that contain routing information for the device (e.g., memory addresses and steering information) to route the data between the memory address of the host system and the memory address of the device, bypassing a memory of the PCIe controller.
    Type: Application
    Filed: March 14, 2013
    Publication date: September 18, 2014
    Applicant: LSI CORPORATION
    Inventors: Eugene Saghi, Richard Solomon, Timothy E. Hoglund
  • Patent number: 8832499
    Abstract: Methods and structure are provided for trapping incoming requests directed to hardware registers of an electronic device. The electronic device that comprises a set of hardware registers that define a configuration of the electronic device, circuitry that implements programmable logic defining which hardware registers have been flagged for trapping incoming requests, and a shadow memory that includes values corresponding to the flagged hardware registers. The circuitry is further operable to access a value in shadow memory that corresponds to a flagged hardware register, responsive to receiving a request from an external device to access the flagged hardware register.
    Type: Grant
    Filed: August 6, 2012
    Date of Patent: September 9, 2014
    Assignee: LSI Corporation
    Inventors: Eugene Saghi, Richard Solomon
  • Publication number: 20140250246
    Abstract: A dynamically controllable buffering system includes a data buffer that is communicatively coupled between first and second data interfaces and operable to perform as an elasticity first-in-first-out buffer in a first mode and to perform as a store-and-forward buffer in a second mode. The system also includes a controller that is operable to detect data rates of the first and second data interfaces, to operate the data buffer in the first mode when the first data interface has a data transfer rate that is faster than a data transfer rate of the second data interface, and to operate the data buffer in the second mode when the second data interface has a data transfer rate that is faster than the data transfer rate of the first data interface.
    Type: Application
    Filed: March 13, 2013
    Publication date: September 4, 2014
    Applicant: LSI CORPORATION
    Inventors: Richard Solomon, Eugene Saghi, John C. Udell
  • Patent number: 8775888
    Abstract: Methods and structure for correlating multiple sets of test output signals in time are provided. The structure includes an integrated circuit comprising a block of circuitry that generates internal operational signals. The circuit also comprises a test multiplexer (MUX) hierarchy that selects subsets of the internal signals and applies the subsets to a testing element. A clock generator generates a clock signal for the selected signals. A test logic timer receives the clock signal and increments a counter value, and applies the counter value to the testing element. An event detector resets the counter value upon detection of an event, such that a first subset of the internal signals acquired from the test MUX hierarchy acquired responsive to detection of a first instance of the event may be correlated in time with a second subset of the internal signals acquired responsive to detection of a second instance of the event.
    Type: Grant
    Filed: March 30, 2012
    Date of Patent: July 8, 2014
    Assignee: LSI Corporation
    Inventors: Eugene Saghi, Jeffrey K. Whitt, Joshua P. Sinykin
  • Patent number: 8745457
    Abstract: Methods and structure are provided for routing internal operational signals of a circuit for output via an external interface. The structure includes an integrated circuit. The integrated circuit comprises a block of circuitry components operable to generate internal operational signals for performing designated functions during normal operation of the circuit, a control unit, a test signal routing hierarchy, and an external interface. The test signal routing hierarchy is coupled to receive the internal operational signals and controllably selects the internal operational signals for acquisition and applies them to the control unit. The external interface provides communications between the integrated circuit and an external device during normal operation of the integrated circuit.
    Type: Grant
    Filed: March 30, 2012
    Date of Patent: June 3, 2014
    Assignee: LSI Corporation
    Inventors: Eugene Saghi, Paul J. Smith, Joshua P. Sinykin, Jeffrey K. Whitt
  • Patent number: 8738979
    Abstract: Methods and structure for correlating internal operational signals routed via different paths of a test signal selection hierarchy. The structure includes a functional block of circuitry operable to generate internal operational signals and clock signals. The integrated circuit also comprises a test signal selection hierarchy operable to receive the internal operational signals and the clock signals and to selectively route the internal operational signals and the clock signals. Further, structure includes a control unit operable to receive the clock signals from the test signal selection hierarchy, to determine a delay between received clock signals routed via different signaling pathways of the test signal selection hierarchy. The control unit is further operable to program a delay line based upon the delay between the clock signals and based upon internal operational signals correlated with the clock signals.
    Type: Grant
    Filed: March 30, 2012
    Date of Patent: May 27, 2014
    Assignee: LSI Corporation
    Inventors: Paul J. Smith, Jeffrey K. Whitt, Eugene Saghi, Douglas J. Saxon, Joshua P. Sinykin
  • Publication number: 20140040672
    Abstract: Methods and structure are provided for trapping incoming requests directed to hardware registers of an electronic device. The electronic device that comprises a set of hardware registers that define a configuration of the electronic device, circuitry that implements programmable logic defining which hardware registers have been flagged for trapping incoming requests, and a shadow memory that includes values corresponding to the flagged hardware registers. The circuitry is further operable to access a value in shadow memory that corresponds to a flagged hardware register, responsive to receiving a request from an external device to access the flagged hardware register.
    Type: Application
    Filed: August 6, 2012
    Publication date: February 6, 2014
    Applicant: LSI CORPORATION
    Inventors: Eugene Saghi, Richard Solomon
  • Publication number: 20130257512
    Abstract: Methods and structure are provided for routing internal operational signals of a circuit for output via an external interface. The structure includes an integrated circuit. The integrated circuit comprises a block of circuitry components operable to generate internal operational signals for performing designated functions during normal operation of the circuit, a control unit, a test signal routing hierarchy, and an external interface. The test signal routing hierarchy is coupled to receive the internal operational signals and controllably selects the internal operational signals for acquisition and applies them to the control unit. The external interface provides communications between the integrated circuit and an external device during normal operation of the integrated circuit.
    Type: Application
    Filed: March 30, 2012
    Publication date: October 3, 2013
    Inventors: Eugene Saghi, Paul J. Smith, Joshua P. Sinykin, Jeffrey K. Whitt
  • Publication number: 20130262945
    Abstract: Methods and structure for correlating multiple sets of test output signals in time are provided. The structure includes an integrated circuit comprising a block of circuitry that generates internal operational signals. The circuit also comprises a test multiplexer (MUX) hierarchy that selects subsets of the internal signals and applies the subsets to a testing element. A clock generator generates a clock signal for the selected signals. A test logic timer receives the clock signal and increments a counter value, and applies the counter value to the testing element. An event detector resets the counter value upon detection of an event, such that a first subset of the internal signals acquired from the test MUX hierarchy acquired responsive to detection of a first instance of the event may be correlated in time with a second subset of the internal signals acquired responsive to detection of a second instance of the event.
    Type: Application
    Filed: March 30, 2012
    Publication date: October 3, 2013
    Inventors: Eugene Saghi, Jeffrey K. Whitt, Joshua P. Sinykin
  • Publication number: 20130262946
    Abstract: Methods and structure for correlating internal operational signals routed via different paths of a test signal selection hierarchy. The structure includes a functional block of circuitry operable to generate internal operational signals and clock signals. The integrated circuit also comprises a test signal selection hierarchy operable to receive the internal operational signals and the clock signals and to selectively route the internal operational signals and the clock signals. Further, structure includes a control unit operable to receive the clock signals from the test signal selection hierarchy, to determine a delay between received clock signals routed via different signaling pathways of the test signal selection hierarchy. The control unit is further operable to program a delay line based upon the delay between the clock signals and based upon internal operational signals correlated with the clock signals.
    Type: Application
    Filed: March 30, 2012
    Publication date: October 3, 2013
    Inventors: Paul J. Smith, Jeffrey K. Whitt, Eugene Saghi, Douglas J. Saxon, Joshua P. Sinykin
  • Patent number: 8176207
    Abstract: An adapter card for testing the functionality of a particular interface configuration may include an interface core. The interface core may comprise an electric circuit including electronic components and control logic for interfacing with an information handling system device. The adapter card may include a front end data channel coupled with the interface core for transmitting data between the electronic components and the information handling system device. The adapter card may include firmware for setting an indicator and causing the control logic to report a memory requirement to the information handling system device larger than a programmed memory space expected by the control logic.
    Type: Grant
    Filed: March 26, 2008
    Date of Patent: May 8, 2012
    Assignee: LSI Corporation
    Inventors: Richard I. Solomon, Jeffrey K. Whitt, Eugene Saghi, Garret Davey