Abstract: In a method of storing data in a nonvolatile memory device, a program operation is performed on target memory cells among a plurality of memory cells based on a program voltage. A verification operation is performed on the target memory cells based on a verification voltage to determine whether all of the target memory cells are completely programmed. The verification voltage is changed depending on the program operation.

Abstract: In a method of storing data in a nonvolatile memory device, a program operation is performed on target memory cells among a plurality of memory cells based on a program voltage. A verification operation is performed on the target memory cells based on a verification voltage to determine whether all of the target memory cells are completely programmed. The verification voltage is changed depending on the program operation.

Abstract: A mask read only memory (ROM) and a method of fabricating the same is provided. This mask ROM and related method is capable of reducing the pitch of buried impurity diffusion regions. In the mask ROM fabrication process, a gate insulation layer is formed over a semiconductor substrate, and parallel conductive layer patterns are formed on the gate insulation layer. These conductive layer patterns are separated from each other by a first predetermined interval and extend in the same direction. Ion implantation is then carried out using the conductive layer patterns as a mask to form buried impurity diffusion regions near the semiconductor substrate between the conductive layer patterns. A conductive layer for use in forming word lines is then formed over the entire surface of the resultant structure, and both the conductive layer and the conductive layer patterns are etched so as to form word lines and pad conductive layers.

Abstract: A mask read only memory (ROM) and a method of fabricating the same is provided. This mask ROM and related method is capable of reducing the pitch of buried impurity diffusion regions. In the mask ROM fabrication process, a gate insulation layer is formed over a semiconductor substrate, and parallel conductive layer patterns are formed on the gate insulation layer. These conductive layer patterns are separated from each other by a first predetermined interval and extend in the same direction. Ion implantation is then carried out using the conductive layer patterns as a mask to form buried impurity diffusion regions near the semiconductor substrate between the conductive layer patterns. A conductive layer for use in forming word lines is then formed over the entire surface of the resultant structure, and both the conductive layer and the conductive layer patterns are etched so as to form word lines and pad conductive layers.

Abstract: A nonvolatile memory device is provided in which cell uniformity is significantly improved. The device includes a plurality of burial N+ diffusion layers extending over the surface of a semiconductor substrate. The plurality of burial N+ diffusion layers are the source/drains of cell transistors and the sub bit-lines of the memory cell array. The device additionally includes a plurality of word lines formed over the semiconductor substrate with gate dielectrics interposed therebetween. The plurality of word lines extend perpendicularly to the burial N+ diffusion layers. A plurality of select lines extend parallel to the word lines and selectively transfer external electrical signals via main bit-lines to the sub bit-lines. The main bit-lines extend parallel to said sub bit-lines. Finally, dummy lines extend parallel to the word lines in the spaces between the select lines and the adjacent word lines.

Abstract: There is provided a non-volatile memory device having a multi-bit cell structure. In the non-volatile memory device, a memory cell array includes a plurality of cells of a first conductivity type which has different threshold voltages and are arranged in a matrix on a semiconductor substrate. A bulk region of a second conductivity type opposite to the first conductivity underlies the memory cell array and receives a predetermined back bias voltage when a cell is driven. The threshold voltage difference between states can be sufficiently widened because a state having a high bulk concentration is highly susceptible to a body effect. Therefore, reduction of masks leads to process simplicity, reduced turnaround time, and improved process margin.

Abstract: A NOR-type mask ROM reduces the resistance ratio of buried diffusion layers and improves the drive capacity of bank selection transistors by utilizing sub-bit line selection transistors located near the center of a memory cell array. The sub-bit line selection transistors are connected to a pair of sub-bank selection lines that divide the memory cell array into symmetric upper and lower portions. The bank selection transistors couple alternate sub-bit lines to main bit lines at both ends of the sub-bit lines, thereby forming a dual current path between the main bit lines and the memory cells coupled to the sub-bit lines.