Abstract: A liquid crystal display according to an exemplary embodiment of the present invention includes: a first substrate; a first signal line disposed on the first substrate, a thin film transistor connected with the first signal line, a first color filter and a second color filter disposed on the first substrate; a colored member disposed on the first color filter and the second color filter; and a pixel electrode disposed on the first color filter and the second color filter and the colored member, wherein the first color filter and the second color filter are partially overlapped with each other and the height of the colored member disposed at the overlap between the first color filter and the second color filter is greater than the height of the colored member disposed not at the overlap.

Abstract: The present invention relates to a liquid crystal display. The liquid crystal display includes a first substrate and a second substrate facing each other; a liquid crystal layer interposed between the first substrate and the second substrate; a sealant coupling the first substrate and the second substrate and enclosing the liquid crystal layer; a display signal line arranged on the first substrate and including an end portion; and a first spacer disposed between the end portion of the display signal line and the sealant. The liquid crystal layer includes liquid crystal molecules exhibiting a pretilt alignment with respect to the first and second substrates.

Abstract: A three mask process for forming an LCD substrate includes, depositing in sequence on a base substrate a gate metallic layer, a gate insulation layer and a channel layer. A first photoresist pattern is used to form a gate electrode of a switching device, a channel pattern and a gate line on the gate electrode. A transparent conductive layer and a source metallic layer are deposited in sequence on the base substrate having the channel pattern. A source electrode and a drain electrode of the switching device, a pixel electrode and a source line electronically connected to the drain electrode, are formed by a second photoresist pattern. A first protective insulation layer is formed, and the first protective insulation layer on the pixel electrode is removed by a third photoresist pattern. Therefore, by the three masks process yields a simplified manufacturing process in which the lower portion of the source metallic pattern is not formed and display quality is improved.

Abstract: A liquid crystal display includes: a first gate line; a first data line crossing the first gate line; a first switching element connected with the first gate line and the first data line; a second switching element connected with the first gate line and the first data line; a first liquid crystal capacitor connected with the first switching element; a second liquid crystal capacitor connected with the second switching element; a boost switching element which is turned on during a time period not overlapping a time period during which the first switching element is turned on; and a boost capacitor including a first terminal connected with the boost switching element and a second terminal connected with the first liquid crystal capacitor.

Abstract: A display panel includes a first display substrate, a second display substrate, and a liquid crystal layer. The first display substrate includes a first base substrate having a plurality of display cells, a plurality of data lines, a plurality of gate lines, and a plurality of pixel electrodes. The data lines, the gate lines and the pixel electrodes are respectively separated in each of the display cells. The second display substrate includes a second base substrate, a light blocking pattern corresponding to the data lines and the gate lines, a common electrode facing the pixel electrodes, and a common line overlapping with the blocking pattern. The liquid crystal layer is disposed between the first and second display substrate.

Abstract: An exemplary embodiment of the present invention discloses a display substrate including a pixel connected to a first gate line and a data line. The pixel includes a first sub-pixel including a first liquid crystal capacitor and a first switching element including a gate electrode connected to the first gate line, a source electrode connected to the data line, and a drain electrode connected to the first liquid crystal capacitor. The pixel also includes a second sub-pixel including a second liquid crystal capacitor and a second switching element including a gate electrode connected to the first gate line, a source electrode connected to the data line, and a drain electrode connected to the second liquid crystal capacitor. The pixel further includes a controller including a control capacitor and a control switching element, the control switching element connected between a terminal of the control capacitor and the drain electrode of the second switching element.

Abstract: A display substrate and a display device are provided. The display substrate includes a substrate having a shielding area and a pixel area, and a black matrix layer disposed in the shielding area of the substrate and having a column spacer and a peripheral portion other than the column spacer, wherein an area of the peripheral portion of the black matrix layer relative to unit pixel area is approximately 11% or less.

Abstract: An array substrate includes a switching element, a signal transmission line, a passivation layer and a pixel electrode. The switching element is disposed on an insulating substrate. The signal transmission line is connected to the switching element and includes a barrier layer, a conductive line, and a copper nitride layer. The barrier layer is disposed on the insulating substrate. The conductive line is disposed on the barrier layer and includes copper or copper alloy. The copper nitride layer covers the conductive line. The passivation layer covers the switching element and the signal transmission line and has a contact hole through which a drain electrode of the switching element is partially exposed. The pixel electrode is disposed on the insulating substrate, and is connected to the drain electrode of the switching element through the contact hole.

Abstract: A thin film transistor array substrate comprising a base substrate, a first wire on the base substrate, a first insulating layer on the base substrate to cover the first wire, a semiconductor layer on the first insulating layer, a second insulating layer on the first insulating layer on which the semiconductor layer is formed, and a second wire on the second insulating layer on the second insulating layer is provided, and a portion of the second wire makes contact with the semiconductor layer through the contact hole.

Abstract: A three mask process for forming an LCD substrate includes, depositing in sequence on a base substrate a gate metallic layer, a gate insulation layer and a channel layer. A first photoresist pattern is used to form a gate electrode of a switching device, a channel pattern and a gate line on the gate electrode. A transparent conductive layer and a source metallic layer are deposited in sequence on the base substrate having the channel pattern. A source electrode and a drain electrode of the switching device, a pixel electrode and a source line electronically connected to the drain electrode, are formed by a second photoresist pattern. A first protective insulation layer is formed, and the first protective insulation layer on the pixel electrode is removed by a third photoresist pattern. Therefore, by the three masks process yields a simplified manufacturing process in which the lower portion of the source metallic pattern is not formed and display quality is improved.

Abstract: Provided are a thin-film transistor (TFT) substrate which can facilitate the formation of contact holes and has improved reliability and a method of fabricating the TFT substrate. The TFT substrate includes a gate wiring formed on an insulating substrate; a data wiring defining a pixel region by intersecting the gate wiring, the data wiring including a source electrode and a drain electrode; a plurality of black matrix barrier ribs formed along the boundaries of the pixel region; a color filter formed to cover the pixel region; a pixel electrode formed on the color filter; and a plurality of contact holes formed through the color filter near the corners of the pixel region through which the pixel electrode and the drain electrode contact each other.

Abstract: A liquid crystal display according to an exemplary embodiment of the present invention includes: a first substrate; a first signal line disposed on the first substrate, a thin film transistor connected with the first signal line, a first color filter and a second color filter disposed on the first substrate; a colored member disposed on the first color filter and the second color filter; and a pixel electrode disposed on the first color filter and the second color filter and the colored member, wherein the first color filter and the second color filter are partially overlapped with each other and the height of the colored member disposed at the overlap between the first color filter and the second color filter is greater than the height of the colored member disposed not at the overlap.

Abstract: A three mask process for forming an LCD substrate includes, depositing in sequence on a base substrate a gate metallic layer, a gate insulation layer and a channel layer. A first photoresist pattern is used to form a gate electrode of a switching device, a channel pattern and a gate line on the gate electrode. A transparent conductive layer and a source metallic layer are deposited in sequence on the base substrate having the channel pattern. A source electrode and a drain electrode of the switching device, a pixel electrode and a source line electronically connected to the drain electrode, are formed by a second photoresist pattern. A first protective insulation layer is formed, and the first protective insulation layer on the pixel electrode is removed by a third photoresist pattern. Therefore, by the three masks process yields a simplified manufacturing process in which the lower portion of the source metallic pattern is not formed and display quality is improved.

Abstract: A thin film transistor array panel including a substrate; a display area signal line; a display area thin film transistor; a peripheral area signal line; a black matrix disposed on the display area signal line, the display area thin film transistor, and the peripheral area signal line, the black matrix including a first and a second contact holes exposing the peripheral area signal line; a protrusion member disposed on the peripheral area signal line, the protrusion member overlapping the peripheral area signal line; a transparent connector disposed on the black matrix and within the peripheral area, wherein the transparent connector contacts the peripheral area signal line through at least one of the first and the second contact holes and includes a protrusion within at least one of the first and the second contact holes which corresponds to the protrusion member; and a pixel electrode.

Abstract: Provided are a wire structure, a method for fabricating a wire, a thin film transistor (TFT) substrate and a method for fabricating a TFT substrate. The wire structure includes a barrier layer formed on a substrate and including a copper layer and a copper solid solution layer.

Abstract: A thin-film transistor includes a semiconductor pattern, source and drain electrodes and a gate electrode, the semiconductor pattern is formed on a base substrate, and the semiconductor pattern includes metal oxide. The source and drain electrodes are formed on the semiconductor pattern such that the source and drain electrodes are spaced apart from each other and an outline of the source and drain electrodes is substantially same as an outline of the semiconductor pattern. The gate electrode is disposed in a region between the source and drain electrodes such that portions of the gate electrode are overlapped with the source and drain electrodes. Therefore, leakage current induced by light is minimized. As a result, characteristics of the thin-film transistor are enhanced, after-image is reduced to enhance display quality, and stability of manufacturing process is enhanced.

Abstract: Provided is a method of fabricating a semiconductive oxide thin-film transistor (TFT) substrate. The method includes forming gate wiring on an insulation substrate; and forming a structure in which a semiconductive oxide film pattern and data wiring are stacked on the gate wiring, wherein the semiconductive oxide film pattern is selectively patterned to have channel regions of first thickness and source/drain regions of greater second thickness and where image data is coupled to the source regions by data wiring formed on the source regions. According to a 4-mask embodiment, the data wiring and semiconductive oxide film pattern are defined by a shared etch mask.

Abstract: In a liquid crystal display, an adhesion layer is provided between an insulating substrate and a wiring feature having very low resistance (e.g. a copper gate line). The adhesion layer may have a thickness of 190 to 210 nm. Good adhesion and high light transmittance can be obtained.

Abstract: The present invention relates to a liquid crystal display. The liquid crystal display includes a first substrate and a second substrate facing each other; a liquid crystal layer interposed between the first substrate and the second substrate; a sealant coupling the first substrate and the second substrate and enclosing the liquid crystal layer; a display signal line arranged on the first substrate and including an end portion; and a first spacer disposed between the end portion of the display signal line and the sealant. The liquid crystal layer includes liquid crystal molecules exhibiting a pretilt alignment with respect to the first and second substrates.

Abstract: A thin film transistor substrate and a method of manufacturing the same are disclosed. The method of manufacturing a thin film transistor substrate includes forming a first conductive pattern group including a gate line, a gate electrode, and a lower gate pad electrode on a substrate, forming a gate insulating layer on the substrate on which the first conductive pattern group is formed, forming an oxide semiconductor pattern overlapping the gate electrode on the gate insulating layer, and forming first and second conductive layers on the substrate on which the oxide semiconductor pattern is formed and patterning the first and second conductive layers to form a second conductive pattern group including a data line, a source electrode, a drain electrode, and a data pad.