Patents by Inventor Eung San Cho

Eung San Cho has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10818646
    Abstract: A power device includes a frame having an electrically insulative material, an opening in the electrically insulative material, and an electrical conductor extending through the electrically insulative material. A power stage module fixed in the opening has an output terminal at a first side of the power stage module, and a power terminal, a ground terminal and a plurality of input/output (I/O) terminals at a second side of the power stage module opposite the first side. A passive component has a first terminal attached to the output terminal of the power stage module and a second terminal attached to the electrical conductor of the frame. The passive component has a larger footprint than the power stage module. The frame expands the footprint of the power stage module to accommodate mounting of the passive component to the power device. The frame has a lower interconnect density than the power stage module.
    Type: Grant
    Filed: February 13, 2019
    Date of Patent: October 27, 2020
    Assignee: Infineon Technologies AG
    Inventors: Petteri Palm, Eung San Cho
  • Publication number: 20200258855
    Abstract: A method of manufacturing a semiconductor device is described. The method includes depositing a photoresist layer over a semiconductor substrate. The photoresist layer is patterned to form an opening in the photoresist layer. A copper pillar is formed in the opening. A diffusion barrier layer is formed over the copper pillar and over a photoresist portion of the photoresist layer directly adjoining the opening. A solder structure is deposited over the diffusion barrier layer.
    Type: Application
    Filed: February 7, 2020
    Publication date: August 13, 2020
    Inventors: Carlo Marbella, Swee Guan Chan, Eung San Cho, Navas Khan Oratti Kalandar
  • Publication number: 20200258873
    Abstract: A power device includes a frame having an electrically insulative material, an opening in the electrically insulative material, and an electrical conductor extending through the electrically insulative material. A power stage module fixed in the opening has an output terminal at a first side of the power stage module, and a power terminal, a ground terminal and a plurality of input/output (I/O) terminals at a second side of the power stage module opposite the first side. A passive component has a first terminal attached to the output terminal of the power stage module and a second terminal attached to the electrical conductor of the frame. The passive component has a larger footprint than the power stage module. The frame expands the footprint of the power stage module to accommodate mounting of the passive component to the power device. The frame has a lower interconnect density than the power stage module.
    Type: Application
    Filed: February 13, 2019
    Publication date: August 13, 2020
    Inventors: Petteri Palm, Eung San Cho
  • Patent number: 10700037
    Abstract: In some examples, a device includes a semiconductor element, a layer element, and a single connector element electrically connecting the semiconductor element and the layer element. In some examples, the single connector element includes two or more discrete connector elements, and each discrete connector element of the two or more discrete connector elements electrically connects the semiconductor element and the layer element. In some examples, the single connector element also includes conductive material attached to the two or more discrete connector elements.
    Type: Grant
    Filed: November 13, 2017
    Date of Patent: June 30, 2020
    Assignee: Infineon Technologies AG
    Inventors: Eung San Cho, Thorsten Meyer, Xaver Schloegel, Thomas Behrens, Josef Hoeglauer
  • Patent number: 10692801
    Abstract: A semiconductor device package includes a die pad having a die attach surface, a first lead that is spaced apart and extends away from a first side of the die pad, and a semiconductor die mounted on the die attach surface. The semiconductor die includes a first bond pad disposed on an upper side of the semiconductor die that is opposite the die attach surface. A first clip electrically connects the first lead to the first bond pad. The first bond pad is elongated with first and second longer edge sides that are opposite one another and extend along a length of the first bond pad. The semiconductor die is oriented such that the first and second longer edge sides of the first bond pad are non-parallel to a first current flow direction of the first clip that extends between the first bond pad and the first lead.
    Type: Grant
    Filed: May 31, 2018
    Date of Patent: June 23, 2020
    Assignee: Infineon Technologies Austria AG
    Inventors: Eung San Cho, Chuan Cheah, Jobelito Anjao Guanzon
  • Patent number: 10681819
    Abstract: In one example, a method includes drilling a cavity into each contact pad of one or more contact pads of a first printed circuit board to form one or more cavities. The first printed circuit board includes an embedded integrated circuit and one or more metal layers. The method further includes forming one or more first metal layers for a second printed circuit board below a bottom surface of the first printed circuit board. The method further includes forming an electrically conductive material in the one or more cavities. The electrically conductive material electrically couples the one or more contact pads of the first printed circuit board to the second printed circuit board. The method further includes forming one or more second metal layers for the second printed circuit board above a top surface of the first printed circuit board.
    Type: Grant
    Filed: December 18, 2018
    Date of Patent: June 9, 2020
    Assignee: Infineon Technologies Austria AG
    Inventors: Eung San Cho, Danny Clavette, Darryl Galipeau
  • Patent number: 10666140
    Abstract: In some examples, a device comprises an integrated circuit comprising a first transistor and a second transistor. The device further comprises an inductor comprising a first inductor terminal and a second inductor terminal, wherein the first inductor terminal is electrically connected to the first transistor and the second transistor. The device further comprises at least five electrical connections on a first side of the device.
    Type: Grant
    Filed: August 22, 2016
    Date of Patent: May 26, 2020
    Assignee: Infineon Technologies Americas Corp.
    Inventor: Eung San Cho
  • Publication number: 20200135619
    Abstract: In an embodiment, a semiconductor package includes a package footprint having a plurality of solderable contact pads, a semiconductor device having a first power electrode and a control electrode on a first surface and a second power electrode on a second surface, a redistribution substrate having an insulating board, wherein the first power electrode and the control electrode are mounted on a first major surface of the insulating board and the solderable contact pads of the package footprint are arranged on a second major surface of the insulating board, and a contact clip having a web portion and one or more peripheral rim portions. The web portion is mounted on and electrically coupled to the second power electrode and the peripheral rim portion is mounted on the first major surface of the insulating board.
    Type: Application
    Filed: October 30, 2019
    Publication date: April 30, 2020
    Inventors: Markus Dinkel, Petteri Palm, Eung San Cho, Josef Hoeglauer, Ralf Otremba, Fabian Schnoy
  • Patent number: 10573631
    Abstract: In some examples, a device comprises at least two semiconductor die, wherein each respective semiconductor die of the at least two semiconductor die comprises at least two power transistors, an input node on a first side of the respective semiconductor die, a reference node on the first side of the respective semiconductor die, and a switch node on a second side of the respective semiconductor die. The device further comprises a first conductive element electrically connected to the respective input nodes of the at least two semiconductor die. The device further comprises a second conductive element electrically connected to the respective reference nodes of the at least two semiconductor die.
    Type: Grant
    Filed: August 9, 2018
    Date of Patent: February 25, 2020
    Assignee: Infineon Technologies Americas Corp.
    Inventor: Eung San Cho
  • Publication number: 20190371711
    Abstract: A semiconductor device package includes a die pad having a die attach surface, a first lead that is spaced apart and extends away from a first side of the die pad, and a semiconductor die mounted on the die attach surface. The semiconductor die includes a first bond pad disposed on an upper side of the semiconductor die that is opposite the die attach surface. A first clip electrically connects the first lead to the first bond pad. The first bond pad is elongated with first and second longer edge sides that are opposite one another and extend along a length of the first bond pad. The semiconductor die is oriented such that the first and second longer edge sides of the first bond pad are non-parallel to a first current flow direction of the first clip that extends between the first bond pad and the first lead.
    Type: Application
    Filed: May 31, 2018
    Publication date: December 5, 2019
    Inventors: Eung San Cho, Chuan Cheah, Jobelito Anjao Guanzon
  • Patent number: 10490505
    Abstract: In some examples, a circuit package further includes an insulating layer and a first transistor extending through the insulating layer, where the first transistor includes a first control terminal on a top side of the insulating layer, a first source terminal on the top side of the insulating layer, and a first drain terminal on a bottom side of the insulating layer. The circuit package includes a second transistor extending through the insulating layer, where the second transistor includes a second control terminal on the top side of the insulating layer, a second source terminal on the bottom side of the insulating layer, and a second drain terminal on the top side of the insulating layer.
    Type: Grant
    Filed: October 12, 2017
    Date of Patent: November 26, 2019
    Assignee: Infineon Technologies Americas Corp.
    Inventor: Eung San Cho
  • Patent number: 10332825
    Abstract: In one implementation, a semiconductor package includes an integrated circuit (IC) flip chip mounted on a first patterned conductive carrier, a second patterned conductive carrier situated over the IC, and a magnetic material situated over the second patterned conductive carrier. The semiconductor package also includes a third patterned conductive carrier situated over the magnetic material. The second patterned conductive carrier and the third patterned conductive carrier are electrically coupled so as to form windings of an integrated inductor in the semiconductor package.
    Type: Grant
    Filed: May 20, 2016
    Date of Patent: June 25, 2019
    Assignee: Infineon Technologies Americas Corp.
    Inventors: Eung San Cho, Parviz Parto
  • Publication number: 20190148332
    Abstract: In some examples, a device includes a semiconductor element, a layer element, and a single connector element electrically connecting the semiconductor element and the layer element. In some examples, the single connector element includes two or more discrete connector elements, and each discrete connector element of the two or more discrete connector elements electrically connects the semiconductor element and the layer element. In some examples, the single connector element also includes conductive material attached to the two or more discrete connector elements.
    Type: Application
    Filed: November 13, 2017
    Publication date: May 16, 2019
    Applicant: Infineon Technologies Americas Corp.
    Inventors: Eung San Cho, Thorsten Meyer, Xaver Schloegel, Thomas Behrens, Josef Hoeglauer
  • Publication number: 20190124773
    Abstract: In one example, a method includes drilling a cavity into each contact pad of one or more contact pads of a first printed circuit board to form one or more cavities. The first printed circuit board includes an embedded integrated circuit and one or more metal layers. The method further includes forming one or more first metal layers for a second printed circuit board below a bottom surface of the first printed circuit board. The method further includes forming an electrically conductive material in the one or more cavities. The electrically conductive material electrically couples the one or more contact pads of the first printed circuit board to the second printed circuit board. The method further includes forming one or more second metal layers for the second printed circuit board above a top surface of the first printed circuit board.
    Type: Application
    Filed: December 18, 2018
    Publication date: April 25, 2019
    Applicant: Infineon Technologies Americas Corp.
    Inventors: Eung San Cho, Danny Clavette, Darryl Galipeau
  • Patent number: 10242938
    Abstract: The disclosure is directed to a circuit on a substrate, such as a leadframe package, that includes shunt to measure current. The shunt is an arched conductor positioned to bridge over a die mounted on the package with voltage measurement terminals of the die electrically connected to the shunt. The techniques of this disclosure determine the shunt material, shunt size and shape to accurately control the value of the resistance of the shunt. The arrangement of the die and the shunt may include advantages of maintaining a small package size and allow accurate temperature compensation. The shunt may be long enough to have a measurable resistance that may be used to determine the current through the shunt. In some examples, the arrangement of the die and the shunt may provide additional structural support to the circuit.
    Type: Grant
    Filed: May 16, 2017
    Date of Patent: March 26, 2019
    Assignee: Infineon Technologies Americas Corp.
    Inventors: Eung San Cho, Wolfgang Furtner
  • Patent number: 10204847
    Abstract: In some examples, a device includes a first leadframe segment and a second leadframe segment, wherein the second leadframe segment is electrically isolated from the first leadframe segment. The device further includes at least four transistors comprising at least two high-side transistors electrically connected to the first leadframe segment and at least two low-side transistors electrically connected to the second leadframe segment. The device further includes at least two conductive output elements, wherein each conductive output element of the at least two conductive output elements is electrically connected to a respective high-side transistor of the at least two high-side transistors and a respective low-side transistor of the at least two low-side transistors. The device further includes an integrated circuit electrically connected to a control terminal of each transistor of the at least four transistors.
    Type: Grant
    Filed: October 6, 2016
    Date of Patent: February 12, 2019
    Assignee: Infineon Technologies Americas Corp.
    Inventor: Eung San Cho
  • Patent number: 10204873
    Abstract: In some examples, a device includes a substrate and a conductive pad extending through the substrate, wherein the substrate is coupled to the conductive pad at an interface and the substrate extends laterally from the interface to define a substrate extension. In some examples, the device also includes a semiconductor die mounted on the first side of the substrate. In some examples, the device includes a breakpoint that defines a torque tolerance that is less than a torque tolerance of the device at other points. In some examples, the device is configured to break at the breakpoint in response to force being applied to the substrate extension on the first side of the substrate.
    Type: Grant
    Filed: May 8, 2017
    Date of Patent: February 12, 2019
    Assignee: Infineon Technologies Americas Corp.
    Inventors: Eung San Cho, Chuan Cheah
  • Patent number: 10206286
    Abstract: In one example, a method includes drilling a cavity into each contact pad of one or more contact pads of a first printed circuit board to form one or more cavities. The first printed circuit board includes an embedded integrated circuit and one or more metal layers. The method further includes forming one or more first metal layers for a second printed circuit board below a bottom surface of the first printed circuit board. The method further includes forming an electrically conductive material in the one or more cavities. The electrically conductive material electrically couples the one or more contact pads of the first printed circuit board to the second printed circuit board. The method further includes forming one or more second metal layers for the second printed circuit board above a top surface of the first printed circuit board.
    Type: Grant
    Filed: June 26, 2017
    Date of Patent: February 12, 2019
    Assignee: Infineon Technologies Austria AG
    Inventors: Eung San Cho, Danny Clavette, Darryl Galipeau
  • Publication number: 20180376598
    Abstract: In one example, a method includes drilling a cavity into each contact pad of one or more contact pads of a first printed circuit board to form one or more cavities. The first printed circuit board includes an embedded integrated circuit and one or more metal layers. The method further includes forming one or more first metal layers for a second printed circuit board below a bottom surface of the first printed circuit board. The method further includes forming an electrically conductive material in the one or more cavities. The electrically conductive material electrically couples the one or more contact pads of the first printed circuit board to the second printed circuit board. The method further includes forming one or more second metal layers for the second printed circuit board above a top surface of the first printed circuit board.
    Type: Application
    Filed: June 26, 2017
    Publication date: December 27, 2018
    Applicant: Infineon Technologies Americas Corp.
    Inventors: Eung San Cho, Danny Clavette, Darryl Galipeau
  • Publication number: 20180350789
    Abstract: In some examples, a device comprises at least two semiconductor die, wherein each respective semiconductor die of the at least two semiconductor die comprises at least two power transistors, an input node on a first side of the respective semiconductor die, a reference node on the first side of the respective semiconductor die, and a switch node on a second side of the respective semiconductor die. The device further comprises a first conductive element electrically connected to the respective input nodes of the at least two semiconductor die. The device further comprises a second conductive element electrically connected to the respective reference nodes of the at least two semiconductor die.
    Type: Application
    Filed: August 9, 2018
    Publication date: December 6, 2018
    Inventor: Eung San Cho