Abstract: Lined photoresist structures to facilitate fabricating back end of line (BEOL) interconnects are described. In an embodiment, a hard mask has recesses formed therein, wherein liner structures are variously disposed each on a sidewall of a respective recess. Photobuckets comprising photoresist material are also variously disposed in the recesses. The liner structures variously serve as marginal buffers to mitigate possible effects of misalignment in the exposure of photoresist material to photons or an electron beam. In another embodiment, a recess has disposed therein a liner structure and a photobucket that are both formed by self-assembly of a photoresist-based block-copolymer.

Abstract: In one embodiment, an apparatus includes a first metal layer, a second metal layer above the first metal layer, a first metal via generally perpendicular with and connected to the first metal layer, a second metal via generally perpendicular with and connected to the second metal layer, a third metal via generally perpendicular with and extending through the first metal layer and the second metal layer, a ferroelectric material between the third metal via and the first metal layer and between the third metal via and the second metal layer, and a hard mask material around a portion of the first metal via above the first metal layer and the second metal layer, around a portion of the second metal via above the first metal layer and the second metal layer, and around a portion of the ferroelectric material above the first metal layer and the second metal layer.

Abstract: Contact over active gate structures with metal oxide cap structures are described. In an example, an integrated circuit structure includes a plurality of gate structures above substrate, each of the gate structures including a gate insulating layer thereon. A plurality of conductive trench contact structures is alternating with the plurality of gate structures, each of the conductive trench contact structures including a metal oxide cap structure thereon. An interlayer dielectric material is over the plurality of gate structures and over the plurality of conductive trench contact structures. An opening is in the interlayer dielectric material and in a gate insulating layer of a corresponding one of the plurality of gate structures. A conductive via is in the opening, the conductive via in direct contact with the corresponding one of the plurality of gate structures, and the conductive via on a portion of one or more of the metal oxide cap structures.

Abstract: A photoresist is disclosed. The photoresist includes a polymer with one repeating unit and an absorbing unit.

Abstract: Contact over active gate structures with metal oxide cap structures are described. In an example, an integrated circuit structure includes a plurality of gate structures above substrate, each of the gate structures including a gate insulating layer thereon. A plurality of conductive trench contact structures is alternating with the plurality of gate structures, each of the conductive trench contact structures including a metal oxide cap structure thereon. An interlayer dielectric material is over the plurality of gate structures and over the plurality of conductive trench contact structures. An opening is in the interlayer dielectric material and in a gate insulating layer of a corresponding one of the plurality of gate structures. A conductive via is in the opening, the conductive via in direct contact with the corresponding one of the plurality of gate structures, and the conductive via on a portion of one or more of the metal oxide cap structures.

Abstract: Aligned pitch-quartered patterning approaches for lithography edge placement error advanced rectification are described. For example, a method of fabricating a semiconductor structure includes forming a first patterned hardmask on a semiconductor substrate. A second hardmask layer is formed on the semiconductor substrate. A segregated di-block co-polymer is formed on the first patterned hardmask and on the second hardmask layer. Second polymer blocks are removed from the segregated di-block co-polymer. A second patterned hardmask is formed from the second hardmask layer and a plurality of semiconductor fins is formed in the semiconductor substrate using first polymer blocks as a mask. A first fin of the plurality of semiconductor fins is removed. Subsequent to removing the first fin, a second fin of the plurality of semiconductor fins is removed.

Abstract: An interconnect structure is disclosed. The interconnect structure includes a first line of interconnects and a second line of interconnects. The first line of interconnects and the second line of interconnects are staggered. The individual interconnects of the second line of interconnects are laterally offset from individual interconnects of the first line of interconnects. A dielectric material is adjacent to at least a portion of the individual interconnects of at least one of the first line of interconnects and the second line of interconnects.

Abstract: Contact over active gate (COAG) structures with conductive trench contact taps are described. In an example, an integrated circuit structure includes a plurality of gate structures above a substrate, each of the gate structures including a gate insulating layer thereon. A plurality of conductive trench contact structures is alternating with the plurality of gate structures, each of the conductive trench contact structures including a trench insulating layer thereon. One of the plurality of conductive trench contact structures includes a conductive tap structure protruding through the corresponding trench insulating layer. An interlayer dielectric material is above the trench insulating layers and the gate insulating layers. A conductive structure is in direct contact with the conductive tap structure of the one of the plurality of conductive trench contact structures.

Abstract: Contact over active gate (COAG) structures with conductive trench contact taps are described. In an example, an integrated circuit structure includes a plurality of gate structures above a substrate, each of the gate structures including a gate insulating layer thereon. A plurality of conductive trench contact structures is alternating with the plurality of gate structures, each of the conductive trench contact structures including a trench insulating layer thereon. One of the plurality of conductive trench contact structures includes a conductive tap structure protruding through the corresponding trench insulating layer. An interlayer dielectric material is above the trench insulating layers and the gate insulating layers. A conductive structure is in direct contact with the conductive tap structure of the one of the plurality of conductive trench contact structures.

Abstract: Methods and apparatus to improve adhesion between metals and dielectrics in circuit devices are disclosed. An apparatus includes a metal layer, a dielectric layer adjacent the metal layer, and a polymeric bonding layer at an interface between the metal layer and the dielectric layer. A polymer molecule in the polymeric bonding layer including an R1 group, an R2 group, and a polymer chain extending between the R1 group and the R2 group. The R1 group is different than the R2 group. The polymeric bonding layer is bonded to the metal layer via the R1 group. The polymeric bonding layer is bonded to the dielectric layer via the R2 group.

Abstract: An integrated circuit structure includes an active region containing more active semiconductor devices, wherein the active region comprises a first grating of metal and dielectric materials with only vertically aligned structures thereon. A transition region containing inactive structures is adjacent to the active region, wherein the transition region comprises a second grating of metal and dielectric materials having at least one of vertical aligned structures and vertical random structures thereon. Both the active regions and the transition regions have an absence of non-uniform gratings with horizontal parallel polymer sheets thereon.

Abstract: Conductive cap-based approaches for conductive via fabrication is described. In an example, an integrated circuit structure includes a plurality of conductive lines in an ILD layer above a substrate. Each of the conductive lines is recessed relative to an uppermost surface of the ILD layer. A plurality of conductive caps is on corresponding ones of the plurality of conductive lines, in recess regions above each of the plurality of conductive lines. A hardmask layer is on the plurality of conductive caps and on the uppermost surface of the ILD layer. The hardmask layer includes a first hardmask component on and aligned with the plurality of conductive caps, and a second hardmask component on an aligned with regions of the uppermost surface of the ILD layer. A conductive via is in an opening in the hardmask layer and on a conductive cap of one of the plurality of conductive lines.

Abstract: An integrated circuit structure includes a first material block comprising a first block insulator layer and a first multilayer stack on the first block insulator layer, the first multilayer stack comprising interleaved pillar electrodes and insulator layers. A second material block is stacked on the first material block and comprises a second block insulator layer, and a second multilayer stack on the second block insulator layer, the second multilayer stack comprising interleaved pillar electrodes and insulator layers. At least one pillar extends through the first material block and the second material block, wherein the at least one pillar has a top width at a top of the first and second material blocks that is greater than a bottom width at a bottom of the first and second material blocks.

Abstract: Multifunctional molecules for selective polymer formation on conductive surfaces, and the resulting structures, are described. In an example, an integrated circuit structure includes a lower metallization layer including alternating metal lines and dielectric lines above the substrate. A molecular brush layer is on the metal lines of the lower metallization layer, the molecular brush layer including multifunctional molecules. A triblock copolymer layer is above the lower metallization layer. The triblock copolymer layer includes a first segregated block component over the dielectric lines of the lower metallization layer, and alternating second and third segregated block components on the molecular brush layer on the metal lines of the lower metallization layer, where the third segregated block component is photosensitive.

Abstract: Disclosed herein are colored gratings in microelectronic structures. For example, a microelectronic structure may include first conductive structures alternating with second conductive structures, wherein individual ones of the first conductive structures include a bottom portion and a top portion, individual cap structures are on individual ones of the second conductive structures, the bottom portions of the first conductive structures are laterally spaced apart from and aligned with the second conductive structures, and the top portions of the first conductive structures are laterally spaced apart from and aligned with the cap structures. In some embodiments, a microelectronic structure may include one or more unordered lamellar regions laterally spaced apart from and aligned with the first conductive structures.

Abstract: Methods for forming via openings by using a lamellar triblock copolymer, a polymer nanocomposite, and a mixed epitaxy approach are disclosed. An example method includes forming a guiding pattern (e.g., a topographical guiding pattern, chemical guiding pattern, or mixed guiding pattern) on a surface of a layer of an IC device, forming lamellar structures based on the guiding pattern by using the lamellar triblock copolymer or forming cylindrical structures based on the guiding pattern by using the polymer nanocomposite, and forming via openings by removing a lamella from each of at least some of the lamellar structures or removing a nanoparticle from each of at least some of the cylindrical structures.

Abstract: Disclosed herein are guided vias in microelectronic structures. For example, a microelectronic structure may include a metallization layer including a conductive via in contact with a conductive line, wherein a center of a top surface of the conductive via is laterally offset from a center of a bottom surface of the conductive via.

Abstract: An integrated circuit interconnect structure includes a first metallization level including a first metal line having a first sidewall and a second sidewall extending a length in a first direction. A second metal line is adjacent to the first metal line and a dielectric is between the first metal line and the second metal line. A second metallization level is above the first metallization level where the second metallization level includes a third metal line extending a length in a second direction orthogonal to the first direction. The third metal line extends over the first metal line and the second metal line but not beyond the first sidewall. A conductive via is between the first metal line and the third metal line where the conductive via does not extend beyond the first sidewall or beyond the second sidewall.

Abstract: Discussed herein is gate spacing in integrated circuit (IC) structures, as well as related methods and components. For example, in some embodiments, an IC structure may include: a first gate metal having a longitudinal axis; a second gate metal, wherein the longitudinal axis of the first gate metal is aligned with a longitudinal axis of the second gate metal; a first gate contact above the first gate metal; a second gate contact above the second gate metal; and an unordered region having an unordered lamellar pattern, wherein the unordered region is coplanar with the first gate contact and the second gate contact.

Abstract: Contact over active gate (COAG) structures are described. In an example, an integrated circuit structure includes a plurality of gate structures above substrate, each of the gate structures including a gate insulating layer thereon. A plurality of conductive trench contact structures is alternating with the plurality of gate structures, each of the conductive trench contact structures including a trench insulating layer thereon. A remnant of a di-block-co-polymer is over a portion of the plurality of gate structures or the plurality of conductive trench contact structures. An interlayer dielectric material is over the di-block-co-polymer, over the plurality of gate structures, and over the plurality of conductive trench contact structures. An opening in the interlayer dielectric material. A conductive structure is in the opening, the conductive structure in direct contact with a corresponding one of the trench contact structures or with a corresponding one of the gate contact structures.