Abstract: A sub-stage for a charge pump includes a dc input pin, a dc output pin, a first radio frequency (rf) input pin configured to receive a first differential signal, a second rf input pin configured to receive a second differential signal, a first transistor having first, second and third terminals, a second transistor having first, second and third terminals, a first bias voltage source, and a second bias voltage source. The third terminal of the first transistor is configured to receive the second differential signal from the second rf input pin and a first offset voltage signal from the first bias voltage source. The third terminal of the second transistor is configured to receive the second differential signal from the second rf input pin and a second offset voltage signal from the second bias voltage source.

Abstract: A circuit (12) comprises a first circuit point (13) and a second circuit point (14), which first circuit point (13) and second circuit point (14) are designed to be connected with RF transmission means (11) being designed for receiving in a contact-less manner a carrier signal (CS) from a read/write station and for feeding the circuit (12) with the received carrier signal (CS). The circuit (12) further comprises circuit testing means (4) being designed to carry out functional tests of the circuit (12) and to output a modulated response signal (TS-MOD) via the first and second circuit points (13, 14) only if the functional tests have been successful.

Abstract: A sub-stage (212) for a charge pump (200) having a first and second phase of operation. The sub-stage (212) comprising a dc input pin (222); a dc output pin (220); a first rf input pin (202) configured to receive a first differential signal; and a second rf input pin (204) configured to receive a second differential signal. The sub-stage (212) further comprising a first transistor (224) having a first, second and third terminal, wherein a current channel is provided between the first and second terminal of the transistor (224); and a second transistor (226) having a first, second and third terminal, wherein a current channel is provided between the first and second terminal of the transistor (226). The first terminal of the first transistor (224) is connected to the dc input pin (222), the second terminal of the first transistor (224) is connected to the first terminal of the second transistor (226), and the second terminal of the second transistor (226) is connected to the dc output pin (220).

Abstract: An electric circuit (30) for generating a clock-sampling signal (CLK) for a sampling device (31) comprises a clock generator (1, 40, 50, 60) for generating a plurality of clock signals (21-24, 51-54, 61-64), a correlation device (L) for correlating a characteristic signal section (LE) of a digital signal (DS) with the plurality of clock signals (21, 22, 23, 24, 51-56, 61-64), and a selecting device (MX) for selecting one of the clock signals (21, 22, 23, 24, 51-55, 61-64) as the clock-sampling signal (CLK) for the sampling device (31) on the basis of the correlation by the correlation device (L). The clock signals (21-24, 51-54, 61-64) have the same cycle duration (T) and are phase-shifted with respect to each other. The sampling device (31) subsequently samples the digital signal (DS) with the clock-sampling signal (CLK).

Abstract: A capacitance system for a radio frequency (RF) charge pump of an RF integrated circuit (IC) includes a fringe capacitor, a second capacitor, and a silicon substrate region. The fringe capacitor is made of backend masks. The second capacitor is located underneath the fringe capacitor. The silicon substrate region is located underneath the second capacitor.

Abstract: A radio frequency interface circuit (11) for a radio frequency identification tag comprising—at least two input terminals (RF+, RF?) for connecting the circuit (10) with an antenna structure of the radio frequency identification tag, —one or more variable resistive loads (14) coupled across pairs of the input terminals (RF+, RF?)—one or more rectifiers (15) each connected on its input side to a pair of input terminals (RF+, RF?) and on its output side to a parallel connection of voltage control means (16) and modulation control means (17), wherein combiner means (18) are provided which are adapted to receive an output signal (19, 20) from the voltage control means (16) and the modulation control means (17), respectively, and to generate a control signal (21) for controlling each variable resistive load (14) depending on the received signals (19, 20) in such a way that each variable resistive load (14) serves as a modulation and voltage regulation circuit, and wherein each variable resistive load is adapted to

Abstract: A data carrier (2) comprises a data circuit (4) arranged on a substrate (3) and data transmission unit (10) being connected to the data circuit (4). The data carrier (2) further comprises at least one strain gauge unit (7) being adapted to measure strains exerted on the substrate (3) and to transmit a deactivating signal (DE) to the data circuit (4) if the measured strains exceed a defined deactivating strain threshold. If the data circuit (4) receives the deactivating signal (DE), the data circuit (4) interrupts a data exchange with an external data reader/writer (1) via the data transmission unit (10).

Abstract: Circuit for a data carrier, which circuit is capable of supplying identification information to a communications arrangement.

Abstract: A data carrier (2) comprises a data circuit (4) arranged on a substrate (3) and data transmission means (10) being connected to the data circuit (4). The data carrier (2) further comprises at least one strain gauge means (7) being adapted to measure strains exerted on the substrate (3) and to transmit a deactivating signal (DE) to the data circuit (4) if the measured strains exceed a defined deactivating strain threshold. If the data circuit (4) receives the deactivating signal (DE), the data circuit (4) interrupts a data exchange with an external data reader/writer (1) via the data transmission means (10).

Abstract: In a method for the determination of disconnection time information (DTI) significant for an inadequate power supply of an integrated circuit (2) of a data carrier (1) such as an RFID-tag. The disconnection time information (DTI) is determined on the basis of the discharge behavior of a first storage capacitor (C1), which is affected by the IC material and by radiation, and the determined disconnection time information (DTI) is corrected in dependence on the effects of the IC material and/or on at least one radiation effect.

Abstract: An exemplary embodiment of the invention provides a charge pump stage (100) that comprises a first input node (101), a second input node (107), a decoupling capacity (109) having a first terminal (108) and a second terminal (110). Further, the charge pump stage (100) comprises a pump control circuit having a first contact node (102) and a second contact node (111), wherein the first input node (101) is coupled to the first contact node (102). Furthermore, the second input node (107) is coupled to the first terminal (108) of the decoupling capacity (109), and the second terminal (110) of the decoupling capacity (109) is coupled to the second contact node (111) and further coupled to ground (112).

Abstract: A circuit (12) comprises a first circuit point (13) and a second circuit point (14), which first circuit point (13) and second circuit point (14) are designed to be connected with RF transmission means (11) being designed for receiving in a contact-less manner a carrier signal (CS) from a read/write station and for feeding the circuit (12) with the received carrier signal (CS). The circuit (12) further comprises circuit testing means (4) being designed to carry out functional tests of the circuit (12) and to output a modulated response signal (TS-MOD) via the first and second circuit points (13, 14) only if the functional tests have been successful.

Abstract: A circuit for a contact-free data carrier comprises a first circuit point and a second circuit point for connection to transmission means of the data carrier; and supply voltage generating means, which are connected to the first connection circuit point and comprise a supply voltage circuit point and a reference potential circuit point and are designed to generate, based on the received carrier signal, a first supply voltage that can be tapped at the supply voltage circuit point against the reference potential circuit point; and direct current decoupling means, which are connected between the second circuit point and the reference potential circuit point and are designed to inhibit a direct current flow between the second circuit point and the reference potential circuit point; and current conducting means that are connected between the second circuit point and the reference potential circuit point, wherein the current conducting means are designed for the unidirectional conduction of current from the referen

Abstract: A radio frequency interface circuit (11) for a radio frequency identification tag comprising—at least two input terminals (RF+, RF?) for connecting the circuit (10) with an antenna structure of the radio frequency identification tag, —one or more variable resistive loads (14) coupled across pairs of the input terminals (RF+, RF?)—one or more rectifiers (15) each connected on its input side to a pair of input terminals (RF+, RF?) and on its output side to a parallel connection of voltage control means (16) and modulation control means (17), wherein combiner means (18) are provided which are adapted to receive an output signal (19, 20) from the voltage control means (16) and the modulation control means (17), respectively, and to generate a control signal (21) for controlling each variable resistive load (14) depending on the received signals (19, 20) in such a way that each variable resistive load (14) serves as a modulation and voltage regulation circuit, and wherein each variable resistive load is adapted to

Abstract: An electric circuit (30) for generating a clock-sampling signal (CLK) for a sampling device (31) comprises a clock generator (1, 40, 50, 60) for generating a plurality of clock signals (21-24, 51-54, 61-64), a correlation device (L) for correlating a characteristic signal section (LE) of a digital signal (DS) with the plurality of clock signals (21, 22, 23, 24, 51-56, 61-64), and a selecting device (MX) for selecting one of the clock signals (21, 22, 23, 24, 51-55, 61-64) as the clock-sampling signal (CLK) for the sampling device (31) on the basis of the correlation by the correlation device (L). The clock signals (21-24, 51-54, 61-64) have the same cycle duration (T) and are phase-shifted with respect to each other. The sampling device (31) subsequently samples the digital signal (DS) with the clock-sampling signal (CLK).

Abstract: An electric counter circuit (30, 40, 80) comprises a clock generator (1, 54, 111, 120, 130) for generating a plurality of clock signals (21-24, 121-125, 131-134) and a sampling device (32, 81) for sampling the clock signals (21-24, 121-125, 131-134) at a first moment in time when a first characteristic signal section (LE) of a digital signal (DS) appears. Furthermore, the circuit (30, 40, 80) comprises a calculation device (33) for calculating the time between the first moment and a second moment which is later than the first moment. This calculation is based on the clock signals (21-24, 121-125, 131-134) at the first moment and based on the clock signals (21-24, 121-125, 131-134) at the second moment. The clock signals (21-24, 121-125, 131-134) each have the same cycle duration (T) and are phase-shifted with respect to each other.

Abstract: In a data carrier (1) that is arranged to receive a signal (S) in a non-contacting manner, there is provided a circuit (2) that is arranged, by using the signal (S), to generate a supply voltage (V) for parts of the circuit (2), the circuit (2) having a storage stage (5) that is arranged to store information capacitively, the information being represented by a value of an information voltage (UI) arising at the storage stage (5), and the circuit (2) having an information-voltage generating stage (6) that is arranged to receive a control signal (CS), which control signal (CS) is of a voltage value that is at most equal to the value of the supply voltage (V), and that is arranged to generate the information voltage (UI) by using the control signal (CS), wherein the information-voltage generating stage (6) has a voltage-raising stage (8) that is arranged to raise the value of the voltage of the control signal (CS).

Abstract: In a method for the determination of disconnection time information (DTI) significant for an inadequate power supply of an integrated circuit (2) of a data carrier (1) such as an RFID-tag. The disconnection time information (DTI) is determined on the basis of the discharge behavior of a first storage capacitor (C1), which is affected by the IC material and by radiation, and the determined disconnection time information (DTI) is corrected in dependence on the effects of the IC material and/or on at least one radiation effect.

Abstract: Circuit for a data carrier, which circuit is capable of supplying identification information to a communications arrangement.

Abstract: In a data carrier (1) that is arranged to receive a signal (S) in a non-contacting manner there is provided a circuit (2) that is arranged, by using the signal (S), to generate a supply voltage (V) for parts of the circuit (2), the circuit (2) has a storage stage (5) that is arranged to store information capacitively, the information being represented by a value of an information voltage (UI) arising at the storage stage (5), which value of the information voltage (UI) is at most equal to the value of the supply voltage (V), and the circuit (2) has an evaluation stage (14) to which the information voltage can be fed and that are arranged to evaluate the information voltage (UI), with the help of a comparison voltage (UC), for the information represented by the information voltage (UI), the comparison-voltage generating stage (15) that is arranged to generate and emit the comparison voltage (UC) being implemented separately from the evaluation stage (14), and the evaluation stage (14) being arranged to receive