Patents by Inventor Eyal Gonen

Eyal Gonen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10310909
    Abstract: Managing execution of computer operations by determining that a computer resource targeted by a command's first operation is available, in a candidate processing record in a processing records schedule, to receive an instruction to perform the first operation, determining that a computer resource targeted by the command's second operation is available, in a processing record in the schedule at a processing offset relative to the candidate record, to receive an instruction to perform the second operation, the processing offset being an expected processing latency associated with the command, scheduling the computer resource targeted by the first operation to receive the instruction to perform the first operation when processing the candidate record in the schedule, and scheduling the computer resource targeted by the second operation to receive the instruction to perform the second operation when processing the processing record in the schedule at the processing offset relative to the candidate record.
    Type: Grant
    Filed: September 12, 2016
    Date of Patent: June 4, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Yiftach Benjamini, Eyal Gonen, Alexander Mesh
  • Patent number: 10310936
    Abstract: Embodiments include a method for temporary pipeline marking for processor error workarounds. The method includes monitoring an execution unit pipeline of a processor for an event associated with a programmable instruction operational code that is predetermined to cause a stuck state resulting in an errant instruction execution. The execution unit pipeline is marked for a workaround action based on detecting the event. A clearing action is triggered based on the marking, where the triggering is conditionally triggered by a next instruction in the execution unit pipeline having a same instruction type as the programmable instruction operational code. The marking of the pipeline is cleared based on the triggering of the clearing action, where the clearing action is a subsequent pipeline flush event based on the next instruction having the same instruction type reaching a same pipeline stage that results in a stuck state prior to completion of the next instruction.
    Type: Grant
    Filed: January 12, 2017
    Date of Patent: June 4, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Erez Barak, Steven R. Carlough, Eyal Gonen, Juergen Haess, Silvia M. Mueller
  • Patent number: 10042764
    Abstract: A method for processing commands in a directory-based computer memory management system includes receiving a command to perform an operation on data stored in a set of one or more computer memory locations associated with an entry in a directory of a computer memory, the entry is associated with an indicator for indicating whether the set of one or more computer memory locations is busy, a head tag, and a tail tag. The command is associated with a command tag and a predecessor tag, and checking the indicator to determine whether the set of one or more computer memory locations is busy.
    Type: Grant
    Filed: June 27, 2016
    Date of Patent: August 7, 2018
    Assignee: International Business Machines Corporation
    Inventors: Michael Bar-Joshua, Yiftach Benjamini, Yaakov Gendel, Eyal Gonen, Alexander Mesh
  • Publication number: 20180074850
    Abstract: Managing execution of computer operations by determining that a computer resource targeted by a command's first operation is available, in a candidate processing record in a processing records schedule, to receive an instruction to perform the first operation, determining that a computer resource targeted by the command's second operation is available, in a processing record in the schedule at a processing offset relative to the candidate record, to receive an instruction to perform the second operation, the processing offset being an expected processing latency associated with the command, scheduling the computer resource targeted by the first operation to receive the instruction to perform the first operation when processing the candidate record in the schedule, and scheduling the computer resource targeted by the second operation to receive the instruction to perform the second operation when processing the processing record in the schedule at the processing offset relative to the candidate record.
    Type: Application
    Filed: September 12, 2016
    Publication date: March 15, 2018
    Inventors: Yiftach BENJAMINI, Eyal GONEN, Alexander MESH
  • Publication number: 20170371788
    Abstract: A method for processing commands in a directory-based computer memory management system includes receiving a command to perform an operation on data stored in a set of one or more computer memory locations associated with an entry in a directory of a computer memory, the entry is associated with an indicator for indicating whether the set of one or more computer memory locations is busy, a head tag, and a tail tag. The command is associated with a command tag and a predecessor tag, and checking the indicator to determine whether the set of one or more computer memory locations is busy.
    Type: Application
    Filed: June 27, 2016
    Publication date: December 28, 2017
    Inventors: Michael Bar-Joshua, Yiftach Benjamini, Yaakov Gendel, Eyal Gonen, Alexander Mesh
  • Publication number: 20170123924
    Abstract: Embodiments include a method for temporary pipeline marking for processor error workarounds. The method includes monitoring an execution unit pipeline of a processor for an event associated with a programmable instruction operational code that is predetermined to cause a stuck state resulting in an errant instruction execution. The execution unit pipeline is marked for a workaround action based on detecting the event. A clearing action is triggered based on the marking, where the triggering is conditionally triggered by a next instruction in the execution unit pipeline having a same instruction type as the programmable instruction operational code. The marking of the pipeline is cleared based on the triggering of the clearing action, where the clearing action is a subsequent pipeline flush event based on the next instruction having the same instruction type reaching a same pipeline stage that results in a stuck state prior to completion of the next instruction.
    Type: Application
    Filed: January 12, 2017
    Publication date: May 4, 2017
    Inventors: Erez Barak, Steven R. Carlough, Eyal Gonen, Juergen Haess, Silvia M. Mueller
  • Patent number: 9588852
    Abstract: Embodiments include a method for temporary pipeline marking for processor error workarounds. The method includes monitoring a pipeline of a processor for an event that is predetermined to place the processor in a stuck state that results in an errant instruction execution result due to the stuck state or repeated resource contention causing performance degradation. The pipeline is marked for a workaround action based on detecting the event. A clearing action is triggered based on the marking of the pipeline. The marking of the pipeline is cleared based on the triggering of the clearing action.
    Type: Grant
    Filed: March 9, 2015
    Date of Patent: March 7, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Erez Barak, Steven R. Carlough, Eyal Gonen, Juergen Haess, Silvia M. Mueller
  • Patent number: 9575836
    Abstract: Embodiments include a computer system for temporary pipeline marking for processor error workarounds, the computer system having a processor configured to perform a method. The method includes monitoring a pipeline of the processor for an event that is predetermined to place the processor in a stuck state that results in an errant instruction execution result due to the stuck state or repeated resource contention causing performance degradation. The pipeline is marked for a workaround action based on detecting the event. A clearing action is triggered based on the marking of the pipeline. The marking of the pipeline is cleared based on the triggering of the clearing action.
    Type: Grant
    Filed: August 30, 2016
    Date of Patent: February 21, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Erez Barak, Steven R. Carlough, Eyal Gonen, Juergen Haess, Silvia M. Mueller
  • Publication number: 20160357638
    Abstract: Embodiments include a computer system for temporary pipeline marking for processor error workarounds, the computer system having a processor configured to perform a method. The method includes monitoring a pipeline of the processor for an event that is predetermined to place the processor in a stuck state that results in an errant instruction execution result due to the stuck state or repeated resource contention causing performance degradation. The pipeline is marked for a workaround action based on detecting the event. A clearing action is triggered based on the marking of the pipeline. The marking of the pipeline is cleared based on the triggering of the clearing action.
    Type: Application
    Filed: August 30, 2016
    Publication date: December 8, 2016
    Inventors: Erez Barak, Steven R. Carlough, Eyal Gonen, Juergen Haess, Silvia M. Mueller
  • Patent number: 9507659
    Abstract: Embodiments include a method for temporary pipeline marking for processor error workarounds. The method includes monitoring a pipeline of a processor for an event that is predetermined to place the processor in a stuck state that results in an errant instruction execution result due to the stuck state or repeated resource contention causing performance degradation. The pipeline is marked for a workaround action based on detecting the event. A clearing action is triggered based on the marking of the pipeline. The marking of the pipeline is cleared based on the triggering of the clearing action.
    Type: Grant
    Filed: March 18, 2016
    Date of Patent: November 29, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Erez Barak, Steven R. Carlough, Eyal Gonen, Juergen Haess, Silvia M. Mueller
  • Publication number: 20160266963
    Abstract: Embodiments include a method for temporary pipeline marking for processor error workarounds. The method includes monitoring a pipeline of a processor for an event that is predetermined to place the processor in a stuck state that results in an errant instruction execution result due to the stuck state or repeated resource contention causing performance degradation. The pipeline is marked for a workaround action based on detecting the event. A clearing action is triggered based on the marking of the pipeline. The marking of the pipeline is cleared based on the triggering of the clearing action.
    Type: Application
    Filed: March 18, 2016
    Publication date: September 15, 2016
    Inventors: Erez Barak, Steven R. Carlough, Eyal Gonen, Juergen Haess, Silvia M. Mueller
  • Publication number: 20160266986
    Abstract: Embodiments include a method for temporary pipeline marking for processor error workarounds. The method includes monitoring a pipeline of a processor for an event that is predetermined to place the processor in a stuck state that results in an errant instruction execution result due to the stuck state or repeated resource contention causing performance degradation. The pipeline is marked for a workaround action based on detecting the event. A clearing action is triggered based on the marking of the pipeline. The marking of the pipeline is cleared based on the triggering of the clearing action.
    Type: Application
    Filed: March 9, 2015
    Publication date: September 15, 2016
    Inventors: Erez Barak, Steven R. Carlough, Eyal Gonen, Juergen Haess, Silvia M. Mueller