Patents by Inventor Eyal Naor

Eyal Naor has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190310856
    Abstract: Embodiments of the present invention disclose a method, a computer program product, and a computer system for system for executing instructions, comprising a processor to detect a pair of destructive instructions within a predetermined number of instructions, wherein each instruction from the pair of destructive instructions assigns a value to be stored in a shared target logical register. In addition, the processor can also execute the pair of destructive instructions in an order received, wherein a result of each instruction of the pair of destructive instructions is mapped to a shared physical register. Furthermore, the processor can execute additional instructions based on the result of the pair of destructive instructions stored in the shared physical register.
    Type: Application
    Filed: April 9, 2018
    Publication date: October 10, 2019
    Inventors: Avraham Ayzenfeld, AMIR TURI, EYAL NAOR, Ido Rozenberg
  • Publication number: 20190294544
    Abstract: A first request is received to access a first set of data in a first cache. A likelihood that a second request to a second cache for the first set of data will be canceled is determined. Access to the first set of data is completed based on the determining the likelihood that the second request to the second cache for the first set of data will be canceled.
    Type: Application
    Filed: June 10, 2019
    Publication date: September 26, 2019
    Inventors: Willm Hinrichs, Markus Kaltenbach, Eyal Naor, Martin Recktenwald
  • Publication number: 20190294543
    Abstract: A first request is received to access a first set of data in a first cache. A likelihood that a second request to a second cache for the first set of data will be canceled is determined. Access to the first set of data is completed based on the determining the likelihood that the second request to the second cache for the first set of data will be canceled.
    Type: Application
    Filed: June 10, 2019
    Publication date: September 26, 2019
    Inventors: Willm Hinrichs, Markus Kaltenbach, Eyal Naor, Martin Recktenwald
  • Patent number: 10417127
    Abstract: A first request is received to access a first set of data in a first cache. A likelihood that a second request to a second cache for the first set of data will be canceled is determined. Access to the first set of data is completed based on the determining the likelihood that the second request to the second cache for the first set of data will be canceled.
    Type: Grant
    Filed: July 13, 2017
    Date of Patent: September 17, 2019
    Assignee: International Business Machines Corporation
    Inventors: Willm Hinrichs, Markus Kaltenbach, Eyal Naor, Martin Recktenwald
  • Patent number: 10409724
    Abstract: A first request is received to access a first set of data in a first cache. A likelihood that a second request to a second cache for the first set of data will be canceled is determined. Access to the first set of data is completed based on the determining the likelihood that the second request to the second cache for the first set of data will be canceled.
    Type: Grant
    Filed: November 15, 2017
    Date of Patent: September 10, 2019
    Assignee: International Business Machines Corporation
    Inventors: Willm Hinrichs, Markus Kaltenbach, Eyal Naor, Martin Recktenwald
  • Patent number: 10360030
    Abstract: Embodiments of the present disclosure relate to processing a microprocessor instruction by receiving a microprocessor instruction for processing by a microprocessor, and processing the microprocessor instruction in a multi-cycle operation by acquiring a unit of data having a plurality of ordered bits, where the acquiring is performed by the microprocessor during a first clock cycle, and shifting the unit of data by a number of bits, where the shifting is performed by the microprocessor during a second clock cycle subsequent to the first clock cycle.
    Type: Grant
    Filed: December 20, 2017
    Date of Patent: July 23, 2019
    Assignee: International Business Machines Corporation
    Inventors: Eyal Naor, Martin Recktenwald, Christian Zoellin, Aaron Tsai
  • Patent number: 10353707
    Abstract: Embodiments of the present disclosure relate to processing a microprocessor instruction by receiving a microprocessor instruction for processing by a microprocessor, and processing the microprocessor instruction in a multi-cycle operation by acquiring a unit of data having a plurality of ordered bits, where the acquiring is performed by the microprocessor during a first clock cycle, and shifting the unit of data by a number of bits, where the shifting is performed by the microprocessor during a second clock cycle subsequent to the first clock cycle.
    Type: Grant
    Filed: July 12, 2017
    Date of Patent: July 16, 2019
    Assignee: International Business Machines Corporation
    Inventors: Eyal Naor, Martin Recktenwald, Christian Zoellin, Aaron Tsai
  • Publication number: 20190213129
    Abstract: A first request is received to access a first set of data in a first cache. A likelihood that a second request to a second cache for the first set of data will be canceled is determined. Access to the first set of data is completed based on the determining the likelihood that the second request to the second cache for the first set of data will be canceled.
    Type: Application
    Filed: March 19, 2019
    Publication date: July 11, 2019
    Inventors: Willm Hinrichs, Markus Kaltenbach, Eyal Naor, Martin Recktenwald
  • Patent number: 10324815
    Abstract: Error checking for a computer processor design under test. In multiple processing threads, and in accordance with a hardware model of a computer processor design under test, the instructions of multiple instruction sequences corresponding to the processing threads are processed, thereby resulting in an order in which the instructions are processed in accordance with the hardware model, and producing an actual result for each of the instructions. An expected result is determined for any of the instructions in accordance with a reference model of the computer processor design under test and in accordance with the order in which the instructions were processed in accordance with the hardware model. Any of the instructions whose expected result and actual result differ are identified.
    Type: Grant
    Filed: February 14, 2017
    Date of Patent: June 18, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Erez Barak, Oz D. Hershkovitz, Gilad Merran, Eyal Naor
  • Publication number: 20190163481
    Abstract: Examples of techniques for executing instructions out of order are described herein. An example computer-implemented method includes receiving, via a processor, a plurality of instructions to be executed. The method includes sending, via the processor, an instruction to a minimal dependency queue in response to detecting the instruction includes a minimally dependent instruction. The method also includes selecting, via the processor, an instruction from a set of instructions that are eligible to be executed based on a scheme. The method further includes executing, via the processor, the instruction.
    Type: Application
    Filed: November 28, 2017
    Publication date: May 30, 2019
    Inventors: AVRAHAM AYZENFELD, EYAL NAOR, AMIR TURI
  • Publication number: 20190042469
    Abstract: A processor(s) performs a cache access to retrieve data, wherein the cache access by initiating a request that includes an address of a first address type. The cache access includes the processor(s) generating, based on historical data related to the address, a prediction for a location of the data in the cache that is a set identifier of a predicted cache set. The processor(s) concurrently perform a data access to the cache to retrieve sets in the cache. The processor(s) confirm(s) that the retrieved include the predicted cache set. The processor(s) utilize(s) the set identifier to select data from the predicted set.
    Type: Application
    Filed: November 16, 2017
    Publication date: February 7, 2019
    Inventors: Dwifuzi COE, Christian JACOBI, Markus KALTENBACH, Eyal NAOR, Martin RECKTENWALD
  • Publication number: 20190042468
    Abstract: A processor(s) performs a cache access to retrieve data, wherein the cache access by initiating a request that includes an address of a first address type. The cache access includes the processor(s) generating, based on historical data related to the address, a prediction for a location of the data in the cache that is a set identifier of a predicted cache set. The processor(s) concurrently perform a data access to the cache to retrieve sets in the cache. The processor(s) confirm(s) that the retrieved include the predicted cache set. The processor(s) utilize(s) the set identifier to select data from the predicted set.
    Type: Application
    Filed: August 4, 2017
    Publication date: February 7, 2019
    Inventors: Dwifuzi COE, Christian JACOBI, Markus KALTENBACH, Eyal NAOR, Martin RECKTENWALD
  • Publication number: 20190018773
    Abstract: A first request is received to access a first set of data in a first cache. A likelihood that a second request to a second cache for the first set of data will be canceled is determined. Access to the first set of data is completed based on the determining the likelihood that the second request to the second cache for the first set of data will be canceled.
    Type: Application
    Filed: November 15, 2017
    Publication date: January 17, 2019
    Inventors: Willm Hinrichs, Markus Kaltenbach, Eyal Naor, Martin Recktenwald
  • Publication number: 20190018681
    Abstract: Embodiments of the present disclosure relate to processing a microprocessor instruction by receiving a microprocessor instruction for processing by a microprocessor, and processing the microprocessor instruction in a multi-cycle operation by acquiring a unit of data having a plurality of ordered bits, where the acquiring is performed by the microprocessor during a first clock cycle, and shifting the unit of data by a number of bits, where the shifting is performed by the microprocessor during a second clock cycle subsequent to the first clock cycle.
    Type: Application
    Filed: July 12, 2017
    Publication date: January 17, 2019
    Inventors: Eyal Naor, Martin Recktenwald, Christian Zoellin, Aaron Tsai
  • Publication number: 20190018772
    Abstract: A first request is received to access a first set of data in a first cache. A likelihood that a second request to a second cache for the first set of data will be canceled is determined. Access to the first set of data is completed based on the determining the likelihood that the second request to the second cache for the first set of data will be canceled.
    Type: Application
    Filed: July 13, 2017
    Publication date: January 17, 2019
    Inventors: Willm Hinrichs, Markus Kaltenbach, Eyal Naor, Martin Recktenwald
  • Publication number: 20190018682
    Abstract: Embodiments of the present disclosure relate to processing a microprocessor instruction by receiving a microprocessor instruction for processing by a microprocessor, and processing the microprocessor instruction in a multi-cycle operation by acquiring a unit of data having a plurality of ordered bits, where the acquiring is performed by the microprocessor during a first clock cycle, and shifting the unit of data by a number of bits, where the shifting is performed by the microprocessor during a second clock cycle subsequent to the first clock cycle.
    Type: Application
    Filed: December 20, 2017
    Publication date: January 17, 2019
    Inventors: Eyal Naor, Martin Recktenwald, Christian Zoellin, Aaron Tsai
  • Publication number: 20190018683
    Abstract: Embodiments of the present disclosure relate to processing a microprocessor instruction by receiving a microprocessor instruction for processing by a microprocessor, and processing the microprocessor instruction in a multi-cycle operation by acquiring a unit of data having a plurality of ordered bits, where the acquiring is performed by the microprocessor during a first clock cycle, and shifting the unit of data by a number of bits, where the shifting is performed by the microprocessor during a second clock cycle subsequent to the first clock cycle.
    Type: Application
    Filed: December 20, 2017
    Publication date: January 17, 2019
    Inventors: Eyal Naor, Martin Recktenwald, Christian Zoellin, Aaron Tsai
  • Patent number: 10169041
    Abstract: Embodiments of the present disclosure relate to processing a microprocessor instruction by receiving a microprocessor instruction for processing by a microprocessor, and processing the microprocessor instruction in a multi-cycle operation by acquiring a unit of data having a plurality of ordered bits, where the acquiring is performed by the microprocessor during a first clock cycle, and shifting the unit of data by a number of bits, where the shifting is performed by the microprocessor during a second clock cycle subsequent to the first clock cycle.
    Type: Grant
    Filed: December 20, 2017
    Date of Patent: January 1, 2019
    Assignee: International Business Machines Corporation
    Inventors: Eyal Naor, Martin Recktenwald, Christian Zoellin, Aaron Tsai
  • Publication number: 20180232292
    Abstract: Error checking for a computer processor design under test. In multiple processing threads, and in accordance with a hardware model of a computer processor design under test, the instructions of multiple instruction sequences corresponding to the processing threads are processed, thereby resulting in an order in which the instructions are processed in accordance with the hardware model, and producing an actual result for each of the instructions. An expected result is determined for any of the instructions in accordance with a reference model of the computer processor design under test and in accordance with the order in which the instructions were processed in accordance with the hardware model. Any of the instructions whose expected result and actual result differ are identified.
    Type: Application
    Filed: February 14, 2017
    Publication date: August 16, 2018
    Inventors: Erez Barak, Oz D. Hershkovitz, Gilad Merran, Eyal Naor