Patents by Inventor Eyal Naor
Eyal Naor has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11907124Abstract: Aspects include using a shadow copy of a level 1 (L1) cache in a cache hierarchy. A method includes maintaining the shadow copy of the L1 cache in the cache hierarchy. The maintaining includes updating the shadow copy of the L1 cache with memory content changes to the L1 cache a number of pipeline cycles after the L1 cache is updated with the memory content changes.Type: GrantFiled: March 31, 2022Date of Patent: February 20, 2024Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Yair Fried, Aaron Tsai, Eyal Naor, Christian Jacobi, Timothy Bronson, Chung-Lung K. Shum
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Publication number: 20230315631Abstract: Aspects include using a shadow copy of a level 1 (L1) cache in a cache hierarchy. A method includes maintaining the shadow copy of the L1 cache in the cache hierarchy. The maintaining includes updating the shadow copy of the L1 cache with memory content changes to the L1 cache a number of pipeline cycles after the L1 cache is updated with the memory content changes.Type: ApplicationFiled: March 31, 2022Publication date: October 5, 2023Inventors: Yair Fried, Aaron Tsai, Eyal Naor, Christian Jacobi, Timothy Bronson, Chung-Lung K. Shum
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Patent number: 11157281Abstract: Prefetching data by detecting a predefined pattern of register activity of a computer processor by detecting when data, at a memory address pointed to by the sum of an offset value and the contents of a register of the processor during an instruction cycle of the processor, is loaded into the register as a result of processing an instruction, detecting the pattern by detecting when data, at a memory address pointed to by the sum of the offset value and the contents of the register during at least one subsequent instruction cycle, is loaded into the register as a result of again processing the instruction, and prefetching data, into a cache memory of the processor, from a current prefetching memory address, where data, at a memory address pointed to by the sum of the offset value and the contents of the register, is used as the current prefetching memory address.Type: GrantFiled: May 24, 2018Date of Patent: October 26, 2021Assignee: International Business Machines CorporationInventors: Eyal Naor, Yossi Shapira, Yair Fried, Amir Turi
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Patent number: 11144321Abstract: Examples of techniques for store hit multiple load side register for operand store compare are described herein. An aspect includes, based on detecting a store hit multiple load condition in the processor, updating a register of the processor to hold information corresponding to a first store instruction that triggered the detected store hit multiple load condition. Another aspect includes, based on issuing a second store instruction in the processor, determining whether the second store instruction corresponds to the information in the register. Another aspect includes, based on determining that the second store instruction corresponds to the information in the register, tagging the second store instruction with an operand store compare mark.Type: GrantFiled: February 20, 2019Date of Patent: October 12, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Yair Fried, Jonathan Hsieh, Eyal Naor, James Bonanno, Gregory William Alexander
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Patent number: 11029950Abstract: A move data instruction to move data from one location to another location is obtained. Based on obtaining the move data instruction, a determination is made as to whether the data to be moved is located in a buffer. The buffer is configured to maintain the data for use by multiple move data instructions. The buffer is used to move the data from the one location to the other location, based on determining that the data to be moved is in the buffer.Type: GrantFiled: July 3, 2019Date of Patent: June 8, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Yossi Shapira, Yair Fried, Eyal Naor, Amir Turi
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Patent number: 10977040Abstract: Methods, systems and computer program products for heuristically invalidating non-useful entries in an array are provided. Aspects include receiving an instruction that is associated with an operand store compare (OSC) prediction for at least one of a store function and a load function. The OSC prediction is stored in an entry of an OSC history table (OHT). Aspects also include executing the instruction. Responsive to determining, based on the execution of the instruction, that data forwarding did not occur, aspects include incrementing a useless OSC prediction counter. Responsive to determining that the useless OSC prediction counter is equal to a predetermined value, aspects also include invalidating the entry of the OHT associated with the instruction.Type: GrantFiled: February 19, 2019Date of Patent: April 13, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: James Raymond Cuffney, Adam Collura, James Bonanno, Jang-Soo Lee, Eyal Naor, Yair Fried, Brian Robert Prasky
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Patent number: 10970214Abstract: A first request is received to access a first set of data in a first cache. A likelihood that a second request to a second cache for the first set of data will be canceled is determined. Access to the first set of data is completed based on the determining the likelihood that the second request to the second cache for the first set of data will be canceled.Type: GrantFiled: June 10, 2019Date of Patent: April 6, 2021Assignee: International Business Machines CorporationInventors: Willm Hinrichs, Markus Kaltenbach, Eyal Naor, Martin Recktenwald
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Patent number: 10956328Abstract: A first request is received to access a first set of data in a first cache. A likelihood that a second request to a second cache for the first set of data will be canceled is determined. Access to the first set of data is completed based on the determining the likelihood that the second request to the second cache for the first set of data will be canceled.Type: GrantFiled: June 10, 2019Date of Patent: March 23, 2021Assignee: International Business Machines CorporationInventors: Willm Hinrichs, Markus Kaltenbach, Eyal Naor, Martin Recktenwald
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Patent number: 10929142Abstract: Provided are embodiments including a computer-implemented method, system and computer program product for determining precise operand-store-compare (OSC) predictions to avoid false dependencies. Some embodiments include detecting an instruction causing an OSC event, wherein the OSC event is at least one of a store-hit-load event or a load-hit-store event, marking an entry in a queue for the instruction based on the detected OSC event, wherein marking the entry comprises setting a bit and saving a tag in the entry in the queue. Some embodiments also include installing an address for the instruction and the tag in the history table responsive to completing the instruction.Type: GrantFiled: March 20, 2019Date of Patent: February 23, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Gregory William Alexander, James Bonanno, Adam Collura, James Raymond Cuffney, Yair Fried, Jonathan Hsieh, Jang-Soo Lee, Edward Malley, Anthony Saporito, Eyal Naor
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Publication number: 20210004228Abstract: A move data instruction to move data from one location to another location is obtained. Based on obtaining the move data instruction, a determination is made as to whether the data to be moved is located in a buffer. The buffer is configured to maintain the data for use by multiple move data instructions. The buffer is used to move the data from the one location to the other location, based on determining that the data to be moved is in the buffer.Type: ApplicationFiled: July 3, 2019Publication date: January 7, 2021Inventors: Yossi Shapira, Yair Fried, Eyal Naor, Amir Turi
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Publication number: 20200301710Abstract: Provided are embodiments including a computer-implemented method, system and computer program product for determining precise operand-store-compare (OSC) predictions to avoid false dependencies. Some embodiments include detecting an instruction causing an OSC event, wherein the OSC event is at least one of a store-hit-load event or a load-hit-store event, marking an entry in a queue for the instruction based on the detected OSC event, wherein marking the entry comprises setting a bit and saving a tag in the entry in the queue. Some embodiments also include installing an address for the instruction and the tag in the history table responsive to completing the instruction.Type: ApplicationFiled: March 20, 2019Publication date: September 24, 2020Inventors: Gregory William Alexander, James Bonanno, Adam Collura, James Raymond Cuffney, Yair Fried, Jonathan Hsieh, Jang-Soo Lee, Edward Malley, Anthony Saporito, Eyal Naor
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Publication number: 20200264885Abstract: Examples of techniques for store hit multiple load side register for operand store compare are described herein. An aspect includes, based on detecting a store hit multiple load condition in the processor, updating a register of the processor to hold information corresponding to a first store instruction that triggered the detected store hit multiple load condition. Another aspect includes, based on issuing a second store instruction in the processor, determining whether the second store instruction corresponds to the information in the register. Another aspect includes, based on determining that the second store instruction corresponds to the information in the register, tagging the second store instruction with an operand store compare mark.Type: ApplicationFiled: February 20, 2019Publication date: August 20, 2020Inventors: Yair Fried, Jonathan Hsieh, EYAL NAOR, JAMES BONANNO, Gregory William Alexander
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Publication number: 20200264882Abstract: Methods, systems and computer program products for heuristically invalidating non-useful entries in an array are provided. Aspects include receiving an instruction that is associated with an operand store compare (OSC) prediction for at least one of a store function and a load function. The OSC prediction is stored in an entry of an OSC history table (OHT). Aspects also include executing the instruction. Responsive to determining, based on the execution of the instruction, that data forwarding did not occur, aspects include incrementing a useless OSC prediction counter. Responsive to determining that the useless OSC prediction counter is equal to a predetermined value, aspects also include invalidating the entry of the OHT associated with the instruction.Type: ApplicationFiled: February 19, 2019Publication date: August 20, 2020Inventors: JAMES RAYMOND CUFFNEY, ADAM COLLURA, JAMES BONANNO, JANG-SOO LEE, EYAL NAOR, YAIR FRIED, BRIAN ROBERT PRASKY
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Patent number: 10691604Abstract: A processor(s) performs a cache access to retrieve data, wherein the cache access by initiating a request that includes an address of a first address type. The cache access includes the processor(s) generating, based on historical data related to the address, a prediction for a location of the data in the cache that is a set identifier of a predicted cache set. The processor(s) concurrently perform a data access to the cache to retrieve sets in the cache. The processor(s) confirm(s) that the retrieved include the predicted cache set. The processor(s) utilize(s) the set identifier to select data from the predicted set.Type: GrantFiled: November 16, 2017Date of Patent: June 23, 2020Assignee: International Business Machines CorporationInventors: Dwifuzi Coe, Christian Jacobi, Markus Kaltenbach, Eyal Naor, Martin Recktenwald
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Patent number: 10684951Abstract: A processor(s) performs a cache access to retrieve data, wherein the cache access by initiating a request that includes an address of a first address type. The cache access includes the processor(s) generating, based on historical data related to the address, a prediction for a location of the data in the cache that is a set identifier of a predicted cache set. The processor(s) concurrently perform a data access to the cache to retrieve sets in the cache. The processor(s) confirm(s) that the retrieved include the predicted cache set. The processor(s) utilize(s) the set identifier to select data from the predicted set.Type: GrantFiled: August 4, 2017Date of Patent: June 16, 2020Assignee: International Business Machines CorporationInventors: Dwifuzi Coe, Christian Jacobi, Markus Kaltenbach, Eyal Naor, Martin Recktenwald
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Patent number: 10678549Abstract: Examples of techniques for executing instructions out of order are described herein. An example computer-implemented method includes receiving, via a processor, a plurality of instructions to be executed. The method includes sending, via the processor, an instruction to a minimal dependency queue in response to detecting the instruction includes a minimally dependent instruction. The method also includes selecting, via the processor, an instruction from a set of instructions that are eligible to be executed based on a scheme. The method further includes executing, via the processor, the instruction.Type: GrantFiled: November 28, 2017Date of Patent: June 9, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Avraham Ayzenfeld, Eyal Naor, Amir Turi
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Patent number: 10649777Abstract: Prefetching data by determining that a first set of instructions that is processed by a computer processor indicates that a second set of instructions includes multiple iteration groups, where each of the iteration groups includes one or more loop-unrolled instructions, monitoring the second set of instructions as the second set of instructions is processed by the computer processor after the first set of instructions is processed by the computer processor, mapping a corresponding one of the loop-unrolled instructions in each of the iteration groups of the second set of instructions to a stride-tracking record that is shared by the corresponding loop-unrolled instructions, and prefetching data into a cache memory of the computer processor based on the stride-tracking record.Type: GrantFiled: May 14, 2018Date of Patent: May 12, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Yossi Shapira, Eyal Naor, Gregory Miaskovsky, Yair Fried
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Patent number: 10572624Abstract: A computer-implemented method, computerized apparatus and computer program product for modified design debugging using differential trace back. An indication of an interface signal in a time unit in an execution resulting in a value miscompare between a design and a modification thereof is obtained. For each of the design and the modification, a data record detailing each signal value in each time unit, and a structure description detailing all components and interconnections thereamong, are obtained. A suspect root cause of the value miscompare is traced back from the interface signal in the time unit, the tracing back comprising comparing values in the data records of candidate signals selected based on the data records and the structure descriptions.Type: GrantFiled: April 30, 2018Date of Patent: February 25, 2020Assignee: International Business Machines CorporationInventors: Erez Barak, Shlomit Koyfman, Eyal Naor, Ziv Nevo, Osher Yifrach
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Publication number: 20190361810Abstract: Prefetching data by detecting a predefined pattern of register activity of a computer processor by detecting when data, at a memory address pointed to by the sum of an offset value and the contents of a register of the processor during an instruction cycle of the processor, is loaded into the register as a result of processing an instruction, detecting the pattern by detecting when data, at a memory address pointed to by the sum of the offset value and the contents of the register during at least one subsequent instruction cycle, is loaded into the register as a result of again processing the instruction, and prefetching data, into a cache memory of the processor, from a current prefetching memory address, where data, at a memory address pointed to by the sum of the offset value and the contents of the register, is used as the current prefetching memory address.Type: ApplicationFiled: May 24, 2018Publication date: November 28, 2019Inventors: Eyal Naor, Yossi Shapira, Yair Fried, Amir Turi
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Publication number: 20190347103Abstract: Prefetching data by determining that a first set of instructions that is processed by a computer processor indicates that a second set of instructions includes multiple iteration groups, where each of the iteration groups includes one or more loop-unrolled instructions, monitoring the second set of instructions as the second set of instructions is processed by the computer processor after the first set of instructions is processed by the computer processor, mapping a corresponding one of the loop-unrolled instructions in each of the iteration groups of the second set of instructions to a stride-tracking record that is shared by the corresponding loop-unrolled instructions, and prefetching data into a cache memory of the computer processor based on the stride-tracking record.Type: ApplicationFiled: May 14, 2018Publication date: November 14, 2019Inventors: Yossi Shapira, EYAL NAOR, Gregory Miaskovsky, Yair Fried