Patents by Inventor Fabrice Marinet

Fabrice Marinet has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210126000
    Abstract: An integrated circuit includes a memory cell incorporating an antifuse device. The antifuse device includes a state transistor having a control gate and a second gate that is configured to be floating. A dielectric layer between the control gate and the second gate is selectively blown in order to confer a broken-down state on the antifuse device where the second gate is electrically coupled to the control gate for storing a first logic state. Otherwise, the antifuse device is in a non-broken-down state for storing a second logic state.
    Type: Application
    Filed: January 5, 2021
    Publication date: April 29, 2021
    Applicant: STMicroelectronics (Rousset) SAS
    Inventors: Pascal FORNARA, Fabrice MARINET
  • Publication number: 20210091015
    Abstract: An integrated circuit is protected against at attack. An electrically conductive body at floating potential is situated in the integrated circuit. The electrically conductive body has an initial amount of electric charge prior to the attack and functions to collect electric charge as a result of the attack. A detection circuit operates to detect an amount of electric charge collected on the electrically conductive body and determine whether the collected amount is different from the initial amount. If the detected amount of charge is different from the initial amount, a control circuit trigger the taking of a protective action.
    Type: Application
    Filed: December 7, 2020
    Publication date: March 25, 2021
    Applicant: STMicroelectronics (Rousset) SAS
    Inventors: Pascal FORNARA, Fabrice MARINET
  • Patent number: 10943876
    Abstract: An attack on an integrated circuit using a beam of electrically charged particles is detected by collecting charges due to the attack using at least one electrically conductive body that is electrically coupled to the floating gate of a state transistor. Prior to the attack, the state transistor is configured to confer an initial threshold voltage. The collected charges passed to the floating gate cause a modification of the threshold voltage of the state transistor. Detection of the attack is made by determining that the threshold voltage of the state transistor is different from the initial threshold voltage.
    Type: Grant
    Filed: July 24, 2019
    Date of Patent: March 9, 2021
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Fabrice Marinet, Pascal Fornara
  • Patent number: 10923484
    Abstract: An integrated circuit includes a memory cell incorporating an antifuse device. The antifuse device includes a state transistor having a control gate and a second gate that is configured to be floating. A dielectric layer between the control gate and the second gate is selectively blown in order to confer a broken-down state on the antifuse device where the second gate is electrically coupled to the control gate for storing a first logic state. Otherwise, the antifuse device is in a non-broken-down state for storing a second logic state.
    Type: Grant
    Filed: August 20, 2019
    Date of Patent: February 16, 2021
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Pascal Fornara, Fabrice Marinet
  • Publication number: 20210028128
    Abstract: An integrated circuit memory includes a state transistor having a floating gate which stores a respective data value. A device for protecting the data stored in the memory includes a capacitive structure having a first electrically-conducting body coupled to the floating gate of the state transistor, a dielectric body, and a second electrically-conducting body coupled to a ground terminal. The dielectric body is configured, if an aqueous solution is brought into contact with the dielectric body, to electrically couple the floating gate and the ground terminal so as to modify the charge on the floating gate and to lose the corresponding data. Otherwise, the dielectric body is configured to electrically isolate the floating gate and the ground terminal.
    Type: Application
    Filed: July 17, 2020
    Publication date: January 28, 2021
    Applicant: STMicroelectronics (Rousset) SAS
    Inventors: Pascal FORNARA, Fabrice MARINET
  • Publication number: 20210019448
    Abstract: Authenticating a device using processing circuitry that generates fingerprints based on states of a plurality of nodes that are coupled to a plurality of circuits. A first fingerprint is generated at a first time based on first states of the plurality of nodes. A second fingerprint is generated at a second time based on second states of the plurality of nodes, the first fingerprint influencing the second states. Electronic data is obtained from the device to be authenticated. The electronic data is compared with a fingerprint generated and a determination whether to authorize operation of the device is made based on a result of the comparison.
    Type: Application
    Filed: July 14, 2020
    Publication date: January 21, 2021
    Inventors: Marc BENVENISTE, Fabien JOURNET, Fabrice MARINET
  • Patent number: 10886240
    Abstract: An integrated circuit is protected against at attack. An electrically conductive body at floating potential is situated in the integrated circuit. The electrically conductive body has an initial amount of electric charge prior to the attack and functions to collect electric charge as a result of the attack. A detection circuit operates to detect an amount of electric charge collected on the electrically conductive body and determine whether the collected amount is different from the initial amount. If the detected amount of charge is different from the initial amount, a control circuit trigger the taking of a protective action.
    Type: Grant
    Filed: July 22, 2019
    Date of Patent: January 5, 2021
    Assignee: STMicroelectronics (Rousset) SAS
    Inventors: Pascal Fornara, Fabrice Marinet
  • Publication number: 20200394337
    Abstract: An electronic circuit includes an interface, a read-only memory in which encrypted data are stored, and cryptographic circuitry coupled to the interface. In operation, the cryptographic circuitry uses a decryption key received via the interface to decrypt the encrypted data. The electronic circuit performs one or more operations using the decrypted data.
    Type: Application
    Filed: June 5, 2020
    Publication date: December 17, 2020
    Inventor: Fabrice MARINET
  • Publication number: 20200365528
    Abstract: A semiconductor substrate has a front face and a back face. A first contact and a second contact, spaced apart from each other, are located on the front face. An electrically conductive wafer is located on the back face. A detection circuit is configured to detect a thinning of the substrate from the back face. The detection circuit including a measurement circuit that takes a measurement of a resistive value of the substrate between said at least one first contact, said at least one second contact and said electrically conductive wafer. Thinning is detected in response to the measured resistive value.
    Type: Application
    Filed: May 12, 2020
    Publication date: November 19, 2020
    Applicant: STMicroelectronics (Rousset) SAS
    Inventors: Alexandre SARAFIANOS, Fabrice MARINET, Julien DELALLEAU
  • Publication number: 20200310805
    Abstract: The disclosure includes a method of authenticating a processor that includes an arithmetic and logic unit. At least one decoded operand of at least a portion of a to-be-executed opcode is received on a first terminal of the arithmetic and logic unit. A signed instruction is received on a second terminal of the arithmetic and logic unit. The signed instruction combines a decoded instruction of the to-be-executed opcode and a previous calculation result of the arithmetic and logic unit.
    Type: Application
    Filed: March 27, 2020
    Publication date: October 1, 2020
    Inventors: Michael PEETERS, Fabrice MARINET
  • Publication number: 20200313880
    Abstract: An electronic device includes processing circuitry and one or more memories, including a non-volatile memory. Ephemeral cryptographic key generation circuitry, in operation, applies a function to code stored in the non-volatile memory, generating an ephemeral cryptographic key. Cryptographic circuitry coupled between the processing circuitry and the one or more memories, in operation, performs one or more cryptographic operations on data using the generated ephemeral cryptographic key. The device may include a register, which, in operation, temporarily stores the generated ephemeral cryptographic key.
    Type: Application
    Filed: March 19, 2020
    Publication date: October 1, 2020
    Inventors: Fabrice MARINET, Michael PEETERS
  • Publication number: 20200311247
    Abstract: The disclosure includes a method of authenticating a processor that includes an arithmetic and logic unit. At least one decoded operand of at least a portion of a to-be-executed opcode is received on a first terminal of the arithmetic and logic unit. A signed instruction is received on a second terminal of the arithmetic and logic unit. The signed instruction combines a decoded instruction of the to-be-executed opcode and at least one previously-executed opcode.
    Type: Application
    Filed: March 27, 2020
    Publication date: October 1, 2020
    Inventors: Michael PEETERS, Fabrice MARINET
  • Publication number: 20200233815
    Abstract: A non-volatile memory is organized in pages and has a word writing granularity of one or more bytes and a block erasing granularity of one or more pages. Logical addresses are scrambling into physical addresses used to perform operations in the non-volatile memory. The scrambling includes scrambling logical data addresses based on a page structure of the non-volatile memory and scrambling logical code addresses based on a word structure of the non-volatile memory.
    Type: Application
    Filed: April 6, 2020
    Publication date: July 23, 2020
    Inventors: Michael Peeters, Fabrice Marinet, Jean-Louis Modave
  • Publication number: 20200202972
    Abstract: A device includes a first switch, a first irreversibly programmable memory point, and a second irreversibly programmable memory point coupled in parallel with the first irreversibly programmable memory point. The first switch and the parallel combination of the first and second irreversibly programmable memory points are coupled in series between a first node and a second node.
    Type: Application
    Filed: December 10, 2019
    Publication date: June 25, 2020
    Inventors: Stephane Denorme, Philippe Candelier, Joel Damiens, Fabrice Marinet
  • Patent number: 10649916
    Abstract: A non-volatile memory is organized in pages and has a word writing granularity of one or more bytes and a block erasing granularity of one or more pages. Logical addresses are scrambling into physical addresses used to perform operations in the non-volatile memory. The scrambling includes scrambling logical data addresses based on a page structure of the non-volatile memory and scrambling logical code addresses based on a word structure of the non-volatile memory.
    Type: Grant
    Filed: April 13, 2017
    Date of Patent: May 12, 2020
    Assignees: STMicroelectronics (Rousset) SAS, Proton World International N.V.
    Inventors: Michael Peeters, Fabrice Marinet, Jean-Louis Modave
  • Patent number: 10614217
    Abstract: An integrated circuit includes functional circuitry such as a processing core, memory interfaces, cryptographic circuitry, etc. The integrated circuit also includes protection circuitry to protect the functional circuitry of the integrated circuit against attacks by hidden channels. The protection circuitry, for each of a series of successive periods of time, selects a configuration of the functional circuitry from a set of configurations of the functional circuitry, sets a duration of the period of time, and applies the selected configuration of the functional circuitry for the set duration of the period of time.
    Type: Grant
    Filed: July 25, 2017
    Date of Patent: April 7, 2020
    Assignees: STMICROELECTRONICS (ROUSSET) SAS, PROTON WORLD INTERNATIONAL N.V.
    Inventors: Jean-Louis Modave, Fabrice Marinet, Michael Peeters
  • Patent number: 10585738
    Abstract: The disclosure concerns a method implemented by a processing device. The method includes performing a first execution by the processing device of a computing function based on one or more initial parameters stored in a first memory device. The execution of the computing function generates one or more modified values of at least one of the initial parameters, wherein during the first execution the one or more initial parameters are read from the first memory device and the one or more modified values are stored in a second memory device. The method also includes performing a second execution by the processing device of the computing function based on the one or more initial parameters stored in the first memory device.
    Type: Grant
    Filed: January 14, 2016
    Date of Patent: March 10, 2020
    Assignees: PROTON WORLD INTERNATIONAL N.V., STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Fabrice Marinet, Jean-Louis Modave, Gilles Van Assche, Ronny Van Keer
  • Publication number: 20200075611
    Abstract: An integrated circuit includes a memory cell incorporating an antifuse device. The antifuse device includes a state transistor having a control gate and a second gate that is configured to be floating. A dielectric layer between the control gate and the second gate is selectively blown in order to confer a broken-down state on the antifuse device where the second gate is electrically coupled to the control gate for storing a first logic state. Otherwise, the antifuse device is in a non-broken-down state for storing a second logic state.
    Type: Application
    Filed: August 20, 2019
    Publication date: March 5, 2020
    Applicant: STMicroelectronics (Rousset) SAS
    Inventors: Pascal FORNARA, Fabrice MARINET
  • Patent number: 10579832
    Abstract: A method of authenticating a slave device. The method includes initializing, by a host device, a charge retention circuit of the slave device, and receiving, by the host device, an indication of a discharge time of the charge retention circuit. The host device authenticates the slave device based on the received indication of the discharge time of the charge retention device.
    Type: Grant
    Filed: November 26, 2018
    Date of Patent: March 3, 2020
    Assignees: PROTON WORLD INTERNATIONAL N.V., STMICROELECTRONICS (ROUSSET) SAS
    Inventors: Jean-Louis Modave, Fabrice Marinet, Denis Farison
  • Publication number: 20200035623
    Abstract: An integrated circuit is protected against at attack. An electrically conductive body at floating potential is situated in the integrated circuit. The electrically conductive body has an initial amount of electric charge prior to the attack and functions to collect electric charge as a result of the attack. A detection circuit operates to detect an amount of electric charge collected on the electrically conductive body and determine whether the collected amount is different from the initial amount. If the detected amount of charge is different from the initial amount, a control circuit trigger the taking of a protective action.
    Type: Application
    Filed: July 22, 2019
    Publication date: January 30, 2020
    Applicant: STMicroelectronics (Rousset) SAS
    Inventors: Pascal FORNARA, Fabrice MARINET