Abstract: A packet scheduler controls dispatch of packets containing constant bit rate (CBR) or real time variable bit rate (rt-VBR) at an ingress operation of multiplexing the packets into payloads of an asynchronous transfer mode (ATM) bearer virtual circuit connection. Packets can be queued in one of a number of queues according to priority. The scheduler controls assembly of common part sublayer payload data units (CPS-PDU) comprising any unused octets from a previous packet partially dispatched, and whole packets in order of priority. If a holdover timer period expires before a common part sublayer payload data unit is completed, the payload of that data unit is packed with null data; and dispatched. The packet dispatch is controlled so as to match the traffic characteristics of an underlying bearer channel.

Abstract: A common part sublayer (CPS) ATM adaptation device provides an interface between a narrow band network and a broad band network. The adaptation device is functionally partitioned to provide scheduling, prioritization and multiplexing of ingress traffic to the broadband network independently of the adaptation layer (AAL) type of that traffic. The device incorporating ingress and egress paths respectively to and from the broadband network. The egress path provides segregation and delineation of incoming data units on to respective external data ports, and the ingress path incorporates a common memory for payload storage whereby to perform multiplexing at both AAL and ATM layers.

Abstract: A packet scheduler controls dispatch of packets containing constant bit rate (CBR) or real time variable bit rate (rt-VBR) at an ingress operation of multiplexing the packets into payloads of an asynchronous transfer mode (ATM) bearer virtual circuit connection. Packets can be queued in one of a number of queues according to priority. The scheduler controls assembly of common part sublayer payload data units (CPS-PDU) comprising any unused octets from a previous packet partially dispatched, and whole packets in order of priority. If a holdover timer period expires before a common part sublayer payload data unit is completed, the payload of that data unit is packed with null data; and dispatched.

Abstract: A traffic scheduler controls despatch of assembled packets or cells at an adaptation interface of an asynchronous transfer mode (ATM) network supporting a plurality of ATM traffic classes on two or more ATM adaptation layers. The scheduler comprising a distributed hierarchy of individual traffic schedulers one or more at each layer of the hierarchy each dedicated to its own traffic class. An aggregate traffic output at one layer in the hierarchy forms an input to the next layer. The lower level layers of the hierarchy are incorporated in a common part sublayer device and provide feedback to higher layers to control the flow of traffic during periods of congestion.

Abstract: An efficient hierarchical multi-resolution method based on Hierarchical Meshes (HM) supports selective and progressive transmission and rendering of 3D geometric models. Methods are disclosed for generating the HM, for selective and progressive transmission of the details of a geometric model represented by the HM, and for selectively adding or removing details to or from a desired region of the model. A data structure based on the HM is also disclosed. The HM has a tree of patches of progressively higher levels from a leaf level to a root level. Each patch of one level is merged from respective connected patches of the next lower level. The patches are simplified recursively from the leaf level to the root level, such that the patches of each level represent respective regions of the geometric model at a resolution that is progressively reducing from the leaf level to the root level, for selective and progressive transmission and rendering.

Abstract: A method and apparatus for handling persistence measurement of channel associated signaling for a plurality of line circuits, eg, T1, E1, OC3, STM 1 circuits, which extracts channel associated signaling data from a plurality of line circuits; assembles the channel associated signaling data into a data frame; contains the data frame in a suitable carrier, eg, an AAL 0 cell; monitors a continuous stream of the data frames, to check for changes in line status; and generates an event message data frame when a persistent change of line state has been detected. The extracting of associated signaling data may be provided on a separate card to a call control processor, and using separate processor functionality.

Abstract: To obviate inefficient use of bandwidth in a packetised system, such as a broadband ATM domain, the use or amount of header information sent in relation to a channel is restricted by one of two principal mechanisms, as exemplified in FIGS. 3 and 4. First, control information incident to a packet interface (20) is interrogated by a processor (21) to determine (50) packet length requirements. A packet length indicator is then generated (52) for inclusion within a header (44) of a packet. Alternatively, a frame (30) is pre-partitioned (60) into several packets (32-42) having different lengths. An addressed subscriber unit (28) is allocated (64) a particular channel, i.e. at least one particular packet within the frame (30), based on data throughput requirements (62), whereby the location of the packet within the frame inherently identifies the length of the packet. Optionally, the data rate used within that packet may also be identified inherently by the location of the packet within the frame (30).

Abstract: A memory architecture for multiple inputs comprises a common memory structure having a plurality of data locations for storing data units and an input section for providing a plurality of input ports with access to the common memory structure. The input section includes a memory buffer for each input port which can store a number of data units equal to the number of input ports, and a bus allowing each memory buffer to write a plurality of data units across the memory structure at least once during a memory-access cycle. The common memory structure includes a number of memory banks equal to the number of input ports. This structure enables the memory banks to be implemented as low speed devices. The memory architecture is suitable for use in ATM system components.

Abstract: A packet scheduler controls dispatch of packets containing constant bit rate (CBR) or real time variable bit rate (rt-VBR) at an ingress operation of multiplexing the packets into payloads of an asynchronous transfer mode (ATM) bearer virtual circuit connection. Packets can be queued in one of a number of queues according to priority. The scheduler controls assembly of common part sublayer payload data units (CPS-PDU) comprising any unused octets from a previous packet partially dispatched, and whole packets in order of priority. If a holdover timer period expires before a common part sublayer payload data unit is completed, the payload of that data unit is packed with null data; and dispatched. The packet dispatch is controlled so as to match the traffic characteristics of an underlying bearer channel.

Abstract: An arrangement for interfacing between TDM and ATM networks consists of a family of devices that comprises two groups. The first group comprises devices that perform multiplexing, segregation and routing field translation for the respective traffic type. They may also remove or substitute an outermost layer of encapsulation. These first group devices are bi-directional and output buffered with respect to the network. The second device group comprises devices that perform format conversions between the service payload (voice, video or data) and an adaptation layer control format. These second group devices are also bi-directional and buffering depends on the particular function, e.g. real-time, segmentation.

Abstract: An interface arrangement provides interworking between packet (IP), time division multiplex (TDM) and asynchronous (ATM) networks, and incorporates a TDM framer providing an interface to the TDM network, a packet framer providing an interface to the packet network, and ATM adaptation function providing an interface to the ATM network. The ATM adaptation function comprises a set or suite of integrated circuit devices, the devices being partitioned by AAL functions into a first device set arranged to perform a common part sublayer function and a second device set arranged to perform service specific sublayer functions. The composition and nature of the device sets can be chosen to match the traffic types and quality of service requirements.

Abstract: In order to support both signalling processing on a per channel basis and multiple adaptation protocols, an interface (10) is modularised principally by function. Incident channels (60-62, Cho—Chn) are applied to a routing device (16) that consults a connection map (64) to determine an appropriate path, via an interface (90), for signal processing of each channel, as shown in FIG. 2. Modularised processing platforms (70-74) each contain a number of signal processors (80-86), with each processing platform providing an additional level of indirection with respect to channel handling. In this latter respect, one of the signal processors (86) on each platform is assigned to distribute channel processing to appropriately configured other ones of the signal processors and such that signal processing functions may be distributed between the other ones (80-84) of the signal processors.