Abstract: Embodiments of semiconductor devices and methods for forming the semiconductor devices are disclosed. In an example, a method for forming device openings includes forming a material layer over a first region and a second region of a substrate, the first region being adjacent to the second region, forming a mask layer over the material layer, the mask layer covering the first region and the second region, and forming a patterning layer over the mask layer. The patterning layer covers the first region and the second region and including openings corresponding to the first region. The plurality of openings includes a first opening adjacent to a boundary between the first region and the second region and a second opening further away from the boundary. Along a plane parallel to a top surface of the substrate, a size of the first opening is greater than a size of the second opening.

Abstract: Embodiments of semiconductor devices and methods for forming the semiconductor devices are disclosed. In an example, a method for forming device openings includes forming a material layer over a first region and a second region of a substrate, the first region being adjacent to the second region, forming a mask layer over the material layer, the mask layer covering the first region and the second region, and forming a patterning layer over the mask layer. The patterning layer covers the first region and the second region and including openings corresponding to the first region. The plurality of openings includes a first opening adjacent to a boundary between the first region and the second region and a second opening further away from the boundary. Along a plane parallel to a top surface of the substrate, a size of the first opening is greater than a size of the second opening.

Abstract: A semiconductor device includes a first vertically-oriented semiconductor pillar having one or more sidewalls, and a top surface, the first vertically-oriented semiconductor pillar having a first width, a first dielectric material abutted to the one or more sidewalls of the first vertically-oriented semiconductor pillar, and a first conductive structure having a first surface, and having a second width that is greater than the first width, the first conductive structure disposed such that a second portion of its first surface is in electrical contact with the top surface of the first vertically-oriented semiconductor pillar, wherein a first portion of the first surface of the first conductive structure extends laterally beyond the top surface of the first vertically-oriented semiconductor pillar, and the second portion of the first surface is disposed on the first dielectric material.

Abstract: A memory device, having a plurality of first-word-lines, each first-word-line having a first portion, a second portion, and a third portion; a plurality of second-word-lines, each second-word-line having a first portion, a second portion, and a third portion; and a memory array having a first side, a second side laterally opposite the first side, and a third side. The first portions of each first-word-line and each second-word-line are spaced apart from their respective third portions. The second portion of each first-word-line and the second portion of each second-word-line are non-parallel and non-co-linear with their respective first portions and third portions. Each first-word-line is disposed such that its second portion is adjacent to the first side, and each second-word-line is disposed such that its second portion is adjacent to the second side. The memory device further has a plurality of first-side-word-line-pickup-structures, and a plurality of second-side-word-line-pickup-structures.

Abstract: A memory device includes a substrate, a stack over the substrate, and a gate line slit extending along a first direction and dividing the stack into two portions. The stack includes a connection portion that connects the two portions of the stack. The connection portion includes at least two sub-connection portions along a second direction perpendicular to the first direction. The gate line slit includes at least two portions along the first direction. Each sub-connection portion is between adjacent two portions of the gate line slit.

Abstract: A semiconductor device and methods for forming the same are provided. The semiconductor device includes an array of vertical transistors. Each transistor includes a semiconductor body extending in a vertical direction, and a gate structure located adjacent to a sidewall of the semiconductor body. The gate structures of each row of vertical transistors are connected with each other and extend along a first lateral direction to form a word line. A first word line of a first row of vertical transistors is located at a first side of the semiconductor bodies of the first row of vertical transistors along a second lateral direction perpendicular to the first lateral direction; and a second word line of a second row of vertical transistors adjacent to the first row of vertical transistors is located at a second side of the semiconductor bodies of the second row of vertical transistors along the second lateral direction.

Abstract: Methods and structures of a three-dimensional memory device are disclosed. In an example, the memory device comprises a substrate, a stack structure on the substrate, and at least one gate line slit extending along a first direction substantially parallel to a top surface of the substrate, and dividing the stack structure into at least two portions. The stack structure includes at least one connection portion that divides the at least one gate line slit, and conductively connects the at least two portions.

Abstract: Embodiments of semiconductor devices and methods for forming the semiconductor devices are disclosed. In an example, a method for forming device openings includes forming a material layer over a first region and a second region of a substrate, the first region being adjacent to the second region, forming a mask layer over the material layer, the mask layer covering the first region and the second region, and forming a patterning layer over the mask layer. The patterning layer covers the first region and the second region and including openings corresponding to the first region. The plurality of openings includes a first opening adjacent to a boundary between the first region and the second region and a second opening further away from the boundary. Along a plane parallel to a top surface of the substrate, a size of the first opening is greater than a size of the second opening.

Abstract: Embodiments of semiconductor devices and methods for forming the semiconductor devices are disclosed. In an example, a method for forming device openings includes forming a material layer over a first region and a second region of a substrate, the first region being adjacent to the second region, forming a mask layer over the material layer, the mask layer covering the first region and the second region, and forming a patterning layer over the mask layer. The patterning layer covers the first region and the second region and including openings corresponding to the first region. The plurality of openings includes a first opening adjacent to a boundary between the first region and the second region and a second opening further away from the boundary. Along a plane parallel to a top surface of the substrate, a size of the first opening is greater than a size of the second opening.

Abstract: Three-dimensional (3D) memory devices and methods for forming the 3D memory devices are provided. For example, a method for forming a 3D memory device is provided. A dielectric stack including interleaved sacrificial layers and dielectric layers is formed on a substrate. A staircase structure is formed on at least one side of the dielectric stack. Dummy channel holes and dummy source holes extending vertically through the staircase structure are formed. A subset of the dummy channel holes is surrounded by the dummy source holes. A dummy channel structure is formed in each dummy channel hole, and interleaved conductive layers and dielectric layers are formed in the staircase structure by replacing, through the dummy source holes, the sacrificial layers in the staircase structure with the conductive layers. A spacer is formed along a sidewall of each dummy source hole to cover the conductive layers in the staircase structure, and a contact is formed within the spacer in each dummy source hole.

Abstract: Methods and structures of a three-dimensional memory device are disclosed. In an example, the memory device comprises a substrate, a stack structure on the substrate, and at least one gate line slit extending along a first direction substantially parallel to a top surface of the substrate, and dividing the stack structure into at least two portions. The stack structure includes at least one connection portion that divides the at least one gate line slit, and conductively connects the at least two portions.

Abstract: Methods and structures of a three-dimensional memory device are disclosed. In an example, the method comprises: providing a substrate; forming an alternating stack over the substrate, the alternating stack comprising a plurality of tiers of sacrificial layer/insulating layer pairs extending along a first direction substantially parallel to a top surface of the substrate; forming a plurality of tiers of word lines extending along the first direction based on the alternating stack; forming at least one connection portion conductively connecting two or more of the word lines of the plurality of tiers of word lines; and forming at least one metal contact via conductively shared by connected word lines, the at least one metal contact via being connected to at least one metal interconnect.

Abstract: Embodiments of 3D memory devices with a dielectric etch stop layer and methods for forming the same are disclosed. In an example, a method for forming a 3D memory device is disclosed. The method includes forming a dielectric etch stop layer. The dielectric etch stop is disposed on a substrate. The method also includes forming a dielectric stack on the dielectric etch stop layer. The dielectric stack includes a plurality of interleaved dielectric layers and sacrificial layers. The method further includes forming an opening extending vertically through the dielectric stack and extending the opening through the dielectric etch stop layer. In addition, the method includes forming a selective epitaxial growth (SEG) plug at a lower portion of the opening. The SEG plug is disposed on the substrate. Moreover, the method includes forming a channel structure above and in contact with the SEG plug in the opening.

Abstract: Embodiments of a three-dimensional (3D) memory device are provided. A method for forming a 3D memory device is disclosed. A dielectric stack including interleaved sacrificial layers and dielectric layers is formed over a substrate. Channel holes and contact holes are formed through the dielectric stack. The contact holes extend vertically into the substrate and are each surrounded by channel holes of nominally equal lateral distances to the respective contact hole in a plan view. A channel structure is formed in each of the channel holes. A memory stack having interleaved conductive layers and dielectric layers is formed by replacing, through the contact holes, the sacrificial layers in the dielectric stack with the conductive layers. A spacer is formed along a sidewall of each of the contact holes to cover the conductive layers of the memory stack. A contact is formed over the spacer in each of the contact holes. The contact is electrically connected to a common source of the channel structures.

Abstract: Embodiments of semiconductor devices and methods for forming the semiconductor devices are disclosed. In an example, a method for forming device openings includes forming a material layer over a first region and a second region of a substrate, the first region being adjacent to the second region, forming a mask layer over the material layer, the mask layer covering the first region and the second region, and forming a patterning layer over the mask layer. The patterning layer covers the first region and the second region and including openings corresponding to the first region. The plurality of openings includes a first opening adjacent to a boundary between the first region and the second region and a second opening further away from the boundary. Along a plane parallel to a top surface of the substrate, a size of the first opening is greater than a size of the second opening.

Abstract: Embodiments of a three-dimensional (3D) memory device are provided. A method for forming a 3D memory device is disclosed. A dielectric stack including interleaved sacrificial layers and dielectric layers is formed over a substrate. Channel holes and contact holes are formed through the dielectric stack. The contact holes extend vertically into the substrate and are each surrounded by channel holes of nominally equal lateral distances to the respective contact hole in a plan view. A channel structure is formed in each of the channel holes. A memory stack having interleaved conductive layers and dielectric layers is formed by replacing, through the contact holes, the sacrificial layers in the dielectric stack with the conductive layers. A spacer is formed along a sidewall of each of the contact holes to cover the conductive layers of the memory stack. A contact is formed over the spacer in each of the contact holes. The contact is electrically connected to a common source of the channel structures.

Abstract: Three-dimensional (3D) memory devices and methods for forming the 3D memory devices are provided. For example, a method for forming a 3D memory device is provided. A dielectric stack including interleaved sacrificial layers and dielectric layers is formed on a substrate. A staircase structure is formed on at least one side of the dielectric stack. Dummy channel holes and dummy source holes extending vertically through the staircase structure are formed. A subset of the dummy channel holes is surrounded by the dummy source holes. A dummy channel structure is formed in each dummy channel hole, and interleaved conductive layers and dielectric layers are formed in the staircase structure by replacing, through the dummy source holes, the sacrificial layers in the staircase structure with the conductive layers. A spacer is formed along a sidewall of each dummy source hole to cover the conductive layers in the staircase structure, and a contact is formed within the spacer in each dummy source hole.

Abstract: Three-dimensional (3D) memory devices and methods for forming the 3D memory devices are provided. In one example, a 3D memory device includes a substrate, a memory stack including interleaved conductive layers and dielectric layers on the substrate, and a staircase structure on one side of the memory stack. The 3D memory device also includes a staircase contact in the staircase structure and a plurality of dummy source structures each extending vertically through the staircase structure. The plurality of dummy source structures surround the staircase contact.

Abstract: Embodiments of 3D memory devices with a dielectric etch stop layer and methods for forming the same are disclosed. In an example, a method for forming a 3D memory device is disclosed. The method includes forming a dielectric etch stop layer. The dielectric etch stop is disposed on a substrate. The method also includes forming a dielectric stack on the dielectric etch stop layer. The dielectric stack includes a plurality of interleaved dielectric layers and sacrificial layers. The method further includes forming an opening extending vertically through the dielectric stack and extending the opening through the dielectric etch stop layer. In addition, the method includes forming a selective epitaxial growth (SEG) plug at a lower portion of the opening. The SEG plug is disposed on the substrate. Moreover, the method includes forming a channel structure above and in contact with the SEG plug in the opening.

Abstract: Embodiments of a three-dimensional (3D) memory device are provided. The 3D memory device includes a substrate, a memory stack with interleaved conductive layers and dielectric layers over the substrate, an array of channel structures each extending vertically through the memory stack, and a plurality of contact hole structures each extending vertically through the memory stack and electrically connected to a common source of one or more of the channel structures. At least one of the plurality of contact hole structures is surrounded by a plurality of the channel structures of nominally equal lateral distances to the respective contact hole structure.