Patents by Inventor Fang Chan
Fang Chan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12272687Abstract: A semiconductor device package includes a redistribution layer, a plurality of conductive pillars, a reinforcing layer and an encapsulant. The conductive pillars are in direct contact with the first redistribution layer. The reinforcing layer surrounds a lateral surface of the conductive pillars. The encapsulant encapsulates the first redistribution layer and the reinforcing layer. The conductive pillars are separated from each other by the reinforcing layer.Type: GrantFiled: December 6, 2022Date of Patent: April 8, 2025Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Ya Fang Chan, Yuan-Feng Chiang
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Publication number: 20250109344Abstract: A gasifier for converting a carbonaceous feedstock to produce syngas comprising a cone section and a throat section; wherein the throat section comprises a throat refractory material having an inside surface and a substantially cylindrical cooling element having an inner face and an outer face in a radial direction, and a top face and a bottom face in the vertical direction, wherein the inner, outer, top, and bottom faces define a cooling cavity; and wherein the cooling element is in thermal contact with the throat refractory material on the inner face, the top face, and the outer face.Type: ApplicationFiled: September 29, 2023Publication date: April 3, 2025Applicant: Air Products and Chemicals, Inc.Inventors: Yichuan Fang, Guiding Wang, Ganesan Ramachandran, Kevin Michael Sullivan, Qiong Zhou, Yan Zhao, Henry Choisun Chan, John Saunders Stevenson
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Publication number: 20250103274Abstract: An interaction control method for detecting a default object in a real-time image and an electronic device are introduced. The method includes steps of image recognition, interaction area setting, movement detection, and playing execution, wherein a default object, a reference object and a setting object are recognized by artificial intelligence in the real-time image, and the electronic device triggers a preset instruction corresponding to the interaction content corresponding to an interaction area by artificial intelligence to recognize a preset instruction corresponding to the interaction content of an interaction area, and the electronic device executes the preset instruction to play a sound response. A terminal device in communication connection with an electronic device and a non-transitory computer-readable recording medium are further provided.Type: ApplicationFiled: August 27, 2024Publication date: March 27, 2025Applicant: COMPAL ELECTRONICS, INC.Inventors: CHIAO-TSU CHIANG, LI-HSIN CHEN, CHIEH-YU CHAN, SHIU-HANG LIN, MIN WEI, YA-FANG HSU
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Patent number: 12230736Abstract: The present disclosure provides a semiconductor light-emitting device and a semiconductor light-emitting component. The semiconductor light-emitting device includes a substrate, a first semiconductor contact layer, a semiconductor light-emitting stack including an active layer, a first-conductivity-type contact structure, a second semiconductor contact layer, a second-conductivity-type contact structure and a first electrode pad. The first-conductivity-type contact structure is electrically connected to the first semiconductor contact layer. The second-conductivity-type contact structure is electrically connected to the second semiconductor contact layer. The first-conductivity-type contact structure has a first bottom surface and a first top surface, and the active layer has a second bottom surface and a second top surface.Type: GrantFiled: March 24, 2021Date of Patent: February 18, 2025Assignee: EPISTAR CORPORATIONInventors: Jian-Zhi Chen, Yen-Chun Tseng, Hui-Fang Kao, Yao-Ning Chan, Yi-Tang Lai, Yun-Chung Chou, Shih-Chang Lee, Chen Ou
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Publication number: 20250029940Abstract: The present disclosure provides a semiconductor device package. The semiconductor device package includes a dielectric layer. The semiconductor device package further includes an antenna structure disposed in the dielectric layer. The semiconductor device package further includes a semiconductor device disposed on the dielectric layer. The semiconductor device package further includes an encapsulant covering the semiconductor device. The semiconductor device package further includes a conductive pillar having a first portion and a second portion. The first portion surrounded by the encapsulant and the second portion embedded in the dielectric layer.Type: ApplicationFiled: October 1, 2024Publication date: January 23, 2025Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Ya Fang CHAN, Yuan-Feng CHIANG, Po-Wei LU
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Patent number: 12107056Abstract: The present disclosure provides a semiconductor device package. The semiconductor device package includes a dielectric layer. The semiconductor device package further includes an antenna structure disposed in the dielectric layer. The semiconductor device package further includes a semiconductor device disposed on the dielectric layer. The semiconductor device package further includes an encapsulant covering the semiconductor device. The semiconductor device package further includes a conductive pillar having a first portion and a second portion. The first portion surrounded by the encapsulant and the second portion embedded in the dielectric layer.Type: GrantFiled: January 16, 2020Date of Patent: October 1, 2024Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Ya Fang Chan, Yuan-Feng Chiang, Po-Wei Lu
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Publication number: 20240249958Abstract: A method for manufacturing a semiconductor package and an apparatus for flattening a workpiece are provided. The method includes providing a panel over a stage, wherein the panel includes a lower surface facing the stage and an upper surface opposite to the lower surface; applying a first force to a first region of the upper surface of the panel along at least one direction from the panel toward the stage; and transferring the first force from the first region to a second region of the upper surface of the panel different from the first region.Type: ApplicationFiled: January 20, 2023Publication date: July 25, 2024Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Ya Fang CHAN, Cong-Wei CHEN, Kuoching CHENG, Shih-Yu WANG
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Patent number: 11791227Abstract: An electronic device package and a method for manufacturing an electronic device package are provided. The electronic device package includes electronic device structure which includes a first electronic device and a first encapsulant, a second electronic device, and a second encapsulant. The first encapsulant encapsulates the first electronic device. The second electronic device is adjacent to the electronic device structure. The second encapsulant encapsulates the electronic device structure and the second electronic device. A first extension line along a lateral surface of the first electronic device and a second extension line along a lateral surface of the first encapsulant define a first angle, the second extension line along the lateral surface of the first encapsulant and a third extension line along a lateral surface of the second electronic device define a second angle, and the first angle is different from the second angle.Type: GrantFiled: May 11, 2021Date of Patent: October 17, 2023Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Kuoching Cheng, Yuan-Feng Chiang, Ya Fang Chan, Wen-Long Lu, Shih-Yu Wang
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Publication number: 20230094668Abstract: A semiconductor device package includes a redistribution layer, a plurality of conductive pillars, a reinforcing layer and an encapsulant. The conductive pillars are in direct contact with the first redistribution layer. The reinforcing layer surrounds a lateral surface of the conductive pillars. The encapsulant encapsulates the first redistribution layer and the reinforcing layer. The conductive pillars are separated from each other by the reinforcing layer.Type: ApplicationFiled: December 6, 2022Publication date: March 30, 2023Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Ya Fang CHAN, Yuan-Feng CHIANG
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Patent number: 11521958Abstract: A semiconductor device package includes a redistribution layer, a plurality of conductive pillars, a reinforcing layer and an encapsulant. The conductive pillars are in direct contact with the first redistribution layer. The reinforcing layer surrounds a lateral surface of the conductive pillars. The encapsulant encapsulates the first redistribution layer and the reinforcing layer. The conductive pillars are separated from each other by the reinforcing layer.Type: GrantFiled: November 5, 2019Date of Patent: December 6, 2022Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Ya Fang Chan, Yuan-Feng Chiang
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Publication number: 20220367304Abstract: An electronic device package and a method for manufacturing an electronic device package are provided. The electronic device package includes electronic device structure which includes a first electronic device and a first encapsulant, a second electronic device, and a second encapsulant. The first encapsulant encapsulates the first electronic device. The second electronic device is adjacent to the electronic device structure. The second encapsulant encapsulates the electronic device structure and the second electronic device. A first extension line along a lateral surface of the first electronic device and a second extension line along a lateral surface of the first encapsulant define a first angle, the second extension line along the lateral surface of the first encapsulant and a third extension line along a lateral surface of the second electronic device define a second angle, and the first angle is different from the second angle.Type: ApplicationFiled: May 11, 2021Publication date: November 17, 2022Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Kuoching CHENG, Yuan-Feng CHIANG, Ya Fang CHAN, Wen-Long LU, Shih-Yu WANG
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Publication number: 20210225783Abstract: The present disclosure provides a semiconductor device package. The semiconductor device package includes a dielectric layer. The semiconductor device package further includes an antenna structure disposed in the dielectric layer. The semiconductor device package further includes a semiconductor device disposed on the dielectric layer. The semiconductor device package further includes an encapsulant covering the semiconductor device. The semiconductor device package further includes a conductive pillar having a first portion and a second portion. The first portion surrounded by the encapsulant and the second portion embedded in the dielectric layer.Type: ApplicationFiled: January 16, 2020Publication date: July 22, 2021Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Ya Fang CHAN, Yuan-Feng CHIANG, Po-Wei LU
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Patent number: 11056435Abstract: At least some embodiments of the present disclosure relate to a substrate for packaging a semiconductor device package. The substrate comprises a dielectric layer, a first conductive element adjacent to the dielectric layer, a second conductive element adjacent to the dielectric layer, and a third conductive element adjacent to the dielectric layer. The first conductive element has a first central axis in a first direction and a second central axis in a second direction. The first conductive element comprises a first chamfer and a second chamfer adjacent to the first chamfer. The second conductive element has a first central axis in the first direction and a second central axis in the second direction. The third conductive element has a first central axis in the first direction and a second central axis in the second direction. The first central axes of the first, second, and third conductive elements are substantially parallel to one another in the first direction and are misaligned from one another.Type: GrantFiled: November 16, 2017Date of Patent: July 6, 2021Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Cheng-Lin Ho, Chung Chieh Chang, Ya Fang Chan, Chih-Cheng Lee
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Publication number: 20210183723Abstract: A semiconductor heat dissipation structure includes a first semiconductor device including a first active surface and a first back surface opposite to the first active surface, a second semiconductor device including a second active surface and a second back surface opposite to the second active surface, a first heat conductive layer embedded in the first back surface of the first semiconductor device, a second heat conductive layer embedded in the second back surface of the second semiconductor device, and a third heat conductive layer disposed adjoining the first heat conductive layer and extending to the first active surface of the first semiconductor device. The first back surface of the first semiconductor device and the second back surface of the second semiconductor device are in contact with each other. At least a portion of the first heat conductive layer are in contact with the second heat conductive layer.Type: ApplicationFiled: December 17, 2019Publication date: June 17, 2021Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Ya Fang CHAN, Yuan-Feng CHIANG, Po-Wei LU
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Patent number: 11037853Abstract: A semiconductor heat dissipation structure includes a first semiconductor device including a first active surface and a first back surface opposite to the first active surface, a second semiconductor device including a second active surface and a second back surface opposite to the second active surface, a first heat conductive layer embedded in the first back surface of the first semiconductor device, a second heat conductive layer embedded in the second back surface of the second semiconductor device, and a third heat conductive layer disposed adjoining the first heat conductive layer and extending to the first active surface of the first semiconductor device. The first back surface of the first semiconductor device and the second back surface of the second semiconductor device are in contact with each other. At least a portion of the first heat conductive layer are in contact with the second heat conductive layer.Type: GrantFiled: December 17, 2019Date of Patent: June 15, 2021Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Ya Fang Chan, Yuan-Feng Chiang, Po-Wei Lu
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Publication number: 20210134781Abstract: A semiconductor device package includes a redistribution layer, a plurality of conductive pillars, a reinforcing layer and an encapsulant. The conductive pillars are in direct contact with the first redistribution layer. The reinforcing layer surrounds a lateral surface of the conductive pillars. The encapsulant encapsulates the first redistribution layer and the reinforcing layer. The conductive pillars are separated from each other by the reinforcing layer.Type: ApplicationFiled: November 5, 2019Publication date: May 6, 2021Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Ya Fang CHAN, Yuan-Feng CHIANG
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Publication number: 20190148297Abstract: At least some embodiments of the present disclosure relate to a substrate for packaging a semiconductor device package. The substrate comprises a dielectric layer, a first conductive element adjacent to the dielectric layer, a second conductive element adjacent to the dielectric layer, and a third conductive element adjacent to the dielectric layer. The first conductive element has a first central axis in a first direction and a second central axis in a second direction. The first conductive element comprises a first chamfer and a second chamfer adjacent to the first chamfer. The second conductive element has a first central axis in the first direction and a second central axis in the second direction. The third conductive element has a first central axis in the first direction and a second central axis in the second direction. The first central axes of the first, second, and third conductive elements are substantially parallel to one another in the first direction and are misaligned from one another.Type: ApplicationFiled: November 16, 2017Publication date: May 16, 2019Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Cheng-Lin HO, Chung Chieh CHANG, Ya Fang CHAN, Chih-Cheng LEE
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Publication number: 20050256386Abstract: A method of non-invasively measuring venous oxygen saturation, comprising: applying a pressure transducer at a first site on a body, applying a drive signal to the external pressure transducer at a predetermined frequency, to cause a series of pulsations of a predetermined magnitude in the venous blood volume in the vicinity of said first site, applying an oximeter device at a second site on the body, measuring output signals received from said oximeter device, said output signals containing a component representative of the modulation of venous blood volume due to said pulsations, deriving a measure of venous oxygen saturation from the frequency response of said output signals.Type: ApplicationFiled: January 31, 2003Publication date: November 17, 2005Inventors: Fang Chan, Matthew Hayes, Peter Smith
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Patent number: D1058339Type: GrantFiled: June 9, 2022Date of Patent: January 21, 2025Inventors: Yu-Chun Chan, Ching-Fang Chang
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Patent number: D1062026Type: GrantFiled: October 28, 2022Date of Patent: February 11, 2025Assignee: EPISTAR CORPORATIONInventors: Hui-Fang Kao, Yao-Ning Chan, Yi-Tang Lai, Yun-Chung Chou, Shih-Chang Lee, Chen Ou