Patents by Inventor Fang-Ting KUO

Fang-Ting KUO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220140109
    Abstract: A method and structure providing a high-voltage transistor (HVT) including a gate dielectric, where at least part of the gate dielectric is provided within a trench disposed within a substrate. In some aspects, a gate oxide thickness may be controlled by way of a trench depth. By providing the HVT with a gate dielectric formed within a trench, embodiments of the present disclosure provide for the top gate stack surface of the HVT and the top gate stack surface of a low-voltage transistor (LVT), formed on the same substrate, to be substantially co-planar with each other, while providing a thick gate oxide for the HVTs. Further, because the top gate stack surface of HVT and the top gate stack surface of the LVT are substantially co-planar with each other, over polishing of the HVT gate stack can be avoided.
    Type: Application
    Filed: January 14, 2022
    Publication date: May 5, 2022
    Inventors: Anhao CHENG, Fang-Ting KUO
  • Patent number: 11227935
    Abstract: A method and structure providing a high-voltage transistor (HVT) including a gate dielectric, where at least part of the gate dielectric is provided within a trench disposed within a substrate. In some aspects, a gate oxide thickness may be controlled by way of a trench depth. By providing the HVT with a gate dielectric formed within a trench, embodiments of the present disclosure provide for the top gate stack surface of the HVT and the top gate stack surface of a low-voltage transistor (LVT), formed on the same substrate, to be substantially co-planar with each other, while providing a thick gate oxide for the HVTs. Further, because the top gate stack surface of HVT and the top gate stack surface of the LVT are substantially co-planar with each other, over polishing of the HVT gate stack can be avoided.
    Type: Grant
    Filed: September 29, 2019
    Date of Patent: January 18, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Anhao Cheng, Fang-Ting Kuo
  • Publication number: 20210351210
    Abstract: A low noise device includes an isolation feature in a substrate. The low noise device further includes a gate stack over a channel in the substrate, wherein the isolation feature is adjacent to the channel. The low noise device further includes a spacer surrounding a portion of the gate stack, wherein an edge of the gate stack is spaced from an edge of the isolation feature adjacent to the spacer by a distance ranging from a minimum spacing distance to about 0.3 microns (?m).
    Type: Application
    Filed: July 23, 2021
    Publication date: November 11, 2021
    Inventors: Victor Chiang LIANG, Fu-Huan TSAI, Chi-Feng HUANG, Yu-Lin WEI, Fang-Ting KUO, Meng-Chang HO
  • Publication number: 20210305356
    Abstract: The present disclosure is directed to a method for the fabrication of MiM capacitor structures with metallic electrodes having nitrogen-rich metal nitride layers. The method includes depositing a first electrode bilayer on a first interconnect disposed on a substrate, where the first electrode includes a first layer and a second layer with a different nitrogen concentration. The method also includes depositing a dielectric layer on the first electrode bilayer and depositing a second electrode bilayer on the first interconnect where the second electrode includes a third layer and a fourth layer with a different nitrogen concentration. The method further includes patterning the first electrode bilayer, the dielectric layer, and the second electrode bilayer to form a capacitor structure on the first interconnect layer.
    Type: Application
    Filed: March 26, 2020
    Publication date: September 30, 2021
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Anhao CHENG, Fang-Ting KUO, Yen-Yu CHEN
  • Patent number: 11094723
    Abstract: A semiconductor device includes a substrate and an isolation feature. The isolation feature includes a first portion in the substrate, and a second portion extending along a top surface of the substrate, wherein a bottom surface of the second portion is below the top surface of the substrate. The semiconductor device further includes a gate structure over the substrate, wherein the gate structure extends along a top surface of the second portion of the isolation feature.
    Type: Grant
    Filed: January 9, 2020
    Date of Patent: August 17, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Victor Chiang Liang, Fu-Huan Tsai, Fang-Ting Kuo, Meng-Chang Ho, Yu-Lin Wei, Chi-Feng Huang
  • Patent number: 11011556
    Abstract: A method of making a semiconductor device includes etching a substrate to define a trench in a substrate, wherein the trench is adjacent to an active region in the substrate, and etching the substrate includes patterning a mask. The method further includes partially removing the mask to expose a first portion of the active region, wherein the first portion extends a first distance from the trench. The method further includes depositing a dielectric material to fill the trench and cover the first portion of the active region. The method further includes removing the mask, wherein the removing of the mask includes maintaining the dielectric material covering the first portion of the active region. The method further includes forming a gate structure over the active region and over the dielectric material.
    Type: Grant
    Filed: January 9, 2020
    Date of Patent: May 18, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Victor Chiang Liang, Fu-Huan Tsai, Fang-Ting Kuo, Meng-Chang Ho, Yu-Lin Wei, Chi-Feng Huang
  • Publication number: 20200152676
    Abstract: A method of making a semiconductor device includes etching a substrate to define a trench in a substrate, wherein the trench is adjacent to an active region in the substrate, and etching the substrate includes patterning a mask. The method further includes partially removing the mask to expose a first portion of the active region, wherein the first portion extends a first distance from the trench. The method further includes depositing a dielectric material to fill the trench and cover the first portion of the active region. The method further includes removing the mask, wherein the removing of the mask includes maintaining the dielectric material covering the first portion of the active region. The method further includes forming a gate structure over the active region and over the dielectric material.
    Type: Application
    Filed: January 9, 2020
    Publication date: May 14, 2020
    Inventors: Victor Chiang LIANG, Fu-Huan TSAI, Fang-Ting KUO, Meng-Chang HO, Yu-Lin WEI, Chi-Feng HUANG
  • Publication number: 20200144315
    Abstract: A semiconductor device includes a substrate and an isolation feature. The isolation feature includes a first portion in the substrate, and a second portion extending along a top surface of the substrate, wherein a bottom surface of the second portion is below the top surface of the substrate. The semiconductor device further includes a gate structure over the substrate, wherein the gate structure extends along a top surface of the second portion of the isolation feature.
    Type: Application
    Filed: January 9, 2020
    Publication date: May 7, 2020
    Inventors: Victor Chiang LIANG, Fu-Huan TSAI, Fang-Ting KUO, Meng-Chang HO, Yu-Lin WEI, Chi-Feng HUANG
  • Publication number: 20200027964
    Abstract: A method and structure providing a high-voltage transistor (HVT) including a gate dielectric, where at least part of the gate dielectric is provided within a trench disposed within a substrate. In some aspects, a gate oxide thickness may be controlled by way of a trench depth. By providing the HVT with a gate dielectric formed within a trench, embodiments of the present disclosure provide for the top gate stack surface of the HVT and the top gate stack surface of a low-voltage transistor (LVT), formed on the same substrate, to be substantially co-planar with each other, while providing a thick gate oxide for the HVTs. Further, because the top gate stack surface of HVT and the top gate stack surface of the LVT are substantially co-planar with each other, over polishing of the HVT gate stack can be avoided.
    Type: Application
    Filed: September 29, 2019
    Publication date: January 23, 2020
    Inventors: Anhao Cheng, Fang-Ting Kuo
  • Patent number: 10535686
    Abstract: A semiconductor device includes a substrate, wherein the substrate includes a channel region. The semiconductor device further includes an isolation feature in the substrate. The isolation feature includes a first portion in the substrate, and a second portion extending along a top surface of the substrate. The second portion partially covers the channel region. The semiconductor device further includes a gate structure over the substrate, wherein the gate structure partially covers the second portion of the isolation feature.
    Type: Grant
    Filed: April 16, 2018
    Date of Patent: January 14, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Victor Chiang Liang, Fu-Huan Tsai, Fang-Ting Kuo, Meng-Chang Ho, Yu-Lin Wei, Chi-Feng Huang
  • Patent number: 10431664
    Abstract: A method and structure providing a high-voltage transistor (HVT) including a gate dielectric, where at least part of the gate dielectric is provided within a trench disposed within a substrate. In some aspects, a gate oxide thickness may be controlled by way of a trench depth. By providing the HVT with a gate dielectric formed within a trench, embodiments of the present disclosure provide for the top gate stack surface of the HVT and the top gate stack surface of a low-voltage transistor (LVT), formed on the same substrate, to be substantially co-planar with each other, while providing a thick gate oxide for the HVTs. Further, because the top gate stack surface of HVT and the top gate stack surface of the LVT are substantially co-planar with each other, over polishing of the HVT gate stack can be avoided.
    Type: Grant
    Filed: January 31, 2018
    Date of Patent: October 1, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Anhao Cheng, Fang-Ting Kuo
  • Publication number: 20190006488
    Abstract: A method and structure providing a high-voltage transistor (HVT) including a gate dielectric, where at least part of the gate dielectric is provided within a trench disposed within a substrate. In some aspects, a gate oxide thickness may be controlled by way of a trench depth. By providing the HVT with a gate dielectric formed within a trench, embodiments of the present disclosure provide for the top gate stack surface of the HVT and the top gate stack surface of a low-voltage transistor (LVT), formed on the same substrate, to be substantially co-planar with each other, while providing a thick gate oxide for the HVTs. Further, because the top gate stack surface of HVT and the top gate stack surface of the LVT are substantially co-planar with each other, over polishing of the HVT gate stack can be avoided.
    Type: Application
    Filed: January 31, 2018
    Publication date: January 3, 2019
    Inventors: Anhao CHENG, Fang-Ting KUO
  • Patent number: 10157990
    Abstract: A semiconductor device is provided, which includes a substrate, a shallow trench isolation (STI), a gate dielectric structure, a capping structure and a gate structure. The STI is in the substrate and defines an active area of the substrate. The gate dielectric structure is on the active area. The capping structure is adjacent to the gate dielectric structure and at edges of the active area. The gate structure is on the gate dielectric structure and the capping structure. An equivalent oxide thickness of the capping structure is substantially greater than an equivalent oxide thickness of the gate dielectric structure.
    Type: Grant
    Filed: March 13, 2017
    Date of Patent: December 18, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chung-Ming Wang, Fang-Ting Kuo
  • Publication number: 20180233522
    Abstract: A semiconductor device includes a substrate, wherein the substrate includes a channel region. The semiconductor device further includes an isolation feature in the substrate. The isolation feature includes a first portion in the substrate, and a second portion extending along a top surface of the substrate. The second portion partially covers the channel region. The semiconductor device further includes a gate structure over the substrate, wherein the gate structure partially covers the second portion of the isolation feature.
    Type: Application
    Filed: April 16, 2018
    Publication date: August 16, 2018
    Inventors: Victor Chiang LIANG, Fu-Huan TSAI, Fang-Ting KUO, Meng-Chang HO, Yu-Lin WEI, Chi-Feng HUANG
  • Patent number: 10050103
    Abstract: A method of making a metal insulator metal (MIM) capacitor includes forming a copper bulk layer in a base layer, wherein the copper bulk layer includes a hillock extending from a top surface thereof. The method further includes depositing an etch stop layer over the base layer and the copper bulk layer. The method further includes depositing an oxide-based dielectric layer over the etch stop layer. The method further includes forming a capacitor over the oxide-based dielectric layer. The method further includes forming a contact extending through the oxide-based dielectric layer and the etch stop layer to contact the copper bulk layer, wherein the forming of the contact removes the hillock.
    Type: Grant
    Filed: May 25, 2017
    Date of Patent: August 14, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Fang-Ting Kuo, Ren-Wei Xiao, Sheng Yu Lin, Chia-Wei Liu, Chun Hua Chang, Chien-Ying Wu
  • Publication number: 20180166545
    Abstract: A semiconductor device is provided, which includes a substrate, a shallow trench isolation (STI), a gate dielectric structure, a capping structure and a gate structure. The STI is in the substrate and defines an active area of the substrate. The gate dielectric structure is on the active area. The capping structure is adjacent to the gate dielectric structure and at edges of the active area. The gate structure is on the gate dielectric structure and the capping structure. An equivalent oxide thickness of the capping structure is substantially greater than an equivalent oxide thickness of the gate dielectric structure.
    Type: Application
    Filed: March 13, 2017
    Publication date: June 14, 2018
    Inventors: Chung-Ming WANG, Fang-Ting KUO
  • Patent number: 9984971
    Abstract: Various embodiments of mechanisms for forming a slotted metal pad over a TSV in substrate are provided. The dielectric structures in the slotted metal pad reduce dishing effect during planarization of the slotted metal pad. As a result, the risk of having metal stringers in upper metal level(s) caused by the dishing effect is greatly reduced.
    Type: Grant
    Filed: December 27, 2016
    Date of Patent: May 29, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Chuan Tseng, Chia-Wei Liu, Fang-Ting Kuo, Ren-Wei Xiao
  • Patent number: 9947701
    Abstract: A low noise device includes an isolation feature in a substrate. The low noise device further includes a gate stack over a channel in the substrate. The gate stack includes a gate dielectric layer extending over a portion of the isolation feature, and a gate electrode over the gate dielectric layer. The low noise device further includes a charge trapping reducing structure adjacent to the isolation feature. The charge trapping reducing structure is configured to reduce a number of charge carriers adjacent an interface between the isolation feature and the channel.
    Type: Grant
    Filed: February 9, 2017
    Date of Patent: April 17, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Victor Chiang Liang, Fu-Huan Tsai, Fang-Ting Kuo, Meng-Chang Ho, Yu-Lin Wei, Chi-Feng Huang
  • Publication number: 20170345855
    Abstract: A low noise device includes an isolation feature in a substrate. The low noise device further includes a gate stack over a channel in the substrate. The gate stack includes a gate dielectric layer extending over a portion of the isolation feature, and a gate electrode over the gate dielectric layer. The low noise device further includes a charge trapping reducing structure adjacent to the isolation feature. The charge trapping reducing structure is configured to reduce a number of charge carriers adjacent an interface between the isolation feature and the channel.
    Type: Application
    Filed: February 9, 2017
    Publication date: November 30, 2017
    Inventors: Victor Chiang LIANG, Fu-Huan TSAI, Fang-Ting KUO, Meng-Chang HO, Yu-Lin WEI, Chi-Feng HUANG
  • Publication number: 20170263694
    Abstract: A method of making a metal insulator metal (MIM) capacitor includes forming a copper bulk layer in a base layer, wherein the copper bulk layer includes a hillock extending from a top surface thereof. The method further includes depositing an etch stop layer over the base layer and the copper bulk layer. The method further includes depositing an oxide-based dielectric layer over the etch stop layer. The method further includes forming a capacitor over the oxide-based dielectric layer. The method further includes forming a contact extending through the oxide-based dielectric layer and the etch stop layer to contact the copper bulk layer, wherein the forming of the contact removes the hillock.
    Type: Application
    Filed: May 25, 2017
    Publication date: September 14, 2017
    Inventors: Fang-Ting KUO, Ren-Wei XIAO, Sheng Yu LIN, Chia-Wei LIU, Chun Hua CHANG, Chien-Ying WU