Patents by Inventor Farid Nemati

Farid Nemati has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190296016
    Abstract: Some embodiments include gated bipolar junction transistors. The transistors may include a base region between a collector region and an emitter region; with a B-C junction being at an interface of the base region and the collector region, and with a B-E junction being at an interface of the base region and the emitter region. The transistors may include material having a bandgap of at least 1.2 eV within one or more of the base, emitter and collector regions. The gated transistors may include a gate along the base region and spaced from the base region by dielectric material, with the gate not overlapping either the B-C junction or the B-E junction. Some embodiments include memory arrays containing gated bipolar junction transistors. Some embodiments include methods of forming gated bipolar junction transistors.
    Type: Application
    Filed: June 10, 2019
    Publication date: September 26, 2019
    Applicant: Micron Technology, Inc.
    Inventors: Rajesh N. Gupta, Farid Nemati, Scott T. Robins
  • Publication number: 20190286519
    Abstract: In one embodiment, a system includes a memory that includes a live section and a spares section. The live section may be mapped to the address space of the system, and may be accessed in response to memory operations. Once an entry in the live section has been detected as failed, an entry is in the spares section may be allocated to replace the failed entry. During subsequent accesses to the failed entry, the allocated entry may be used instead. In an embodiment, the failed entry may be coded with an indication of the allocated entry, to redirect to the allocated entry. In one implementation, for example, the failed entry may be coded with N copies of a pointer to the allocated entry, each copy protected by corresponding ECC.
    Type: Application
    Filed: May 7, 2019
    Publication date: September 19, 2019
    Inventors: Manu Gulati, Sukalpa Biswas, Jeffrey R. Wilcox, Farid Nemati
  • Patent number: 10373956
    Abstract: Some embodiments include gated bipolar junction transistors. The transistors may include a base region between a collector region and an emitter region; with a B-C junction being at an interface of the base region and the collector region, and with a B-E junction being at an interface of the base region and the emitter region. The transistors may include material having a bandgap of at least 1.2 eV within one or more of the base, emitter and collector regions. The gated transistors may include a gate along the base region and spaced from the base region by dielectric material, with the gate not overlapping either the B-C junction or the B-E junction. Some embodiments include memory arrays containing gated bipolar junction transistors. Some embodiments include methods of forming gated bipolar junction transistors.
    Type: Grant
    Filed: February 4, 2015
    Date of Patent: August 6, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Rajesh N. Gupta, Farid Nemati, Scott T. Robins
  • Publication number: 20190198083
    Abstract: In an embodiment, a memory system may include at least two types of DRAM, which differ in at least one characteristic. For example, one DRAM type may be a high density DRAM, while another DRAM type may have lower density but may also have lower latency and higher bandwidth than the first DRAM type. DRAM of the first type may be on one or more first integrated circuits and DRAM of the second type may be on one or more second integrated circuits. In an embodiment, the first and second integrated circuits may be coupled together in a stack. The second integrated circuit may include a physical layer circuit to couple to other circuitry (e.g. an integrated circuit having a memory controller, such as a system on a chip (SOC)), and the physical layer circuit may be shared by the DRAM in the first integrated circuits.
    Type: Application
    Filed: March 6, 2017
    Publication date: June 27, 2019
    Inventors: Sukalpa Biswasw, Farid Nemati
  • Patent number: 10318377
    Abstract: In one embodiment, a system includes a memory that includes a live section and a spares section. The live section may be mapped to the address space of the system, and may be accessed in response to memory operations. Once an entry in the live section has been detected as failed, an entry is in the spares section may be allocated to replace the failed entry. During subsequent accesses to the failed entry, the allocated entry may be used instead. In an embodiment, the failed entry may be coded with an indication of the allocated entry, to redirect to the allocated entry. In one implementation, for example, the failed entry may be coded with N copies of a pointer to the allocated entry, each copy protected by corresponding ECC.
    Type: Grant
    Filed: July 9, 2018
    Date of Patent: June 11, 2019
    Assignee: Apple Inc.
    Inventors: Manu Gulati, Sukalpa Biswas, Jeffrey R. Wilcox, Farid Nemati
  • Publication number: 20180314592
    Abstract: In one embodiment, a system includes a memory that includes a live section and a spares section. The live section may be mapped to the address space of the system, and may be accessed in response to memory operations. Once an entry in the live section has been detected as failed, an entry is in the spares section may be allocated to replace the failed entry. During subsequent accesses to the failed entry, the allocated entry may be used instead. In an embodiment, the failed entry may be coded with an indication of the allocated entry, to redirect to the allocated entry. In one implementation, for example, the failed entry may be coded with N copies of a pointer to the allocated entry, each copy protected by corresponding ECC.
    Type: Application
    Filed: July 9, 2018
    Publication date: November 1, 2018
    Inventors: Manu Gulati, Sukalpa Biswas, Jeffrey R. Wilcox, Farid Nemati
  • Patent number: 10042701
    Abstract: In one embodiment, a system includes a memory that includes a live section and a spares section. The live section may be mapped to the address space of the system, and may be accessed in response to memory operations. Once an entry in the live section has been detected as failed, an entry is in the spares section may be allocated to replace the failed entry. During subsequent accesses to the failed entry, the allocated entry may be used instead. In an embodiment, the failed entry may be coded with an indication of the allocated entry, to redirect to the allocated entry. In one implementation, for example, the failed entry may be coded with N copies of a pointer to the allocated entry, each copy protected by corresponding ECC.
    Type: Grant
    Filed: September 22, 2016
    Date of Patent: August 7, 2018
    Assignee: Apple Inc.
    Inventors: Manu Gulati, Sukalpa Biswas, Jeffrey R. Wilcox, Farid Nemati
  • Patent number: 9691465
    Abstract: Some embodiments include thyristors having first and second electrode regions, first and second base regions, and material having a bandgap of at least 1.2 eV in at least one of the regions. The first base region is between the first electrode region and the second base region, and the second base region is between the second electrode region and the first base region. The first base region interfaces with the first electrode region at a first junction, and interfaces with the second base region at a second junction. The second base region interfaces with the second electrode region at a third junction. A gate is along the first base region, and in some embodiments does not overlap either of the first and second junctions. Some embodiments include methods of programming thyristors, and some embodiments include methods of forming thyristors.
    Type: Grant
    Filed: November 20, 2015
    Date of Patent: June 27, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Farid Nemati, Scott T. Robins, Rajesh N. Gupta
  • Publication number: 20170091026
    Abstract: In one embodiment, a system includes a memory that includes a live section and a spares section. The live section may be mapped to the address space of the system, and may be accessed in response to memory operations. Once an entry in the live section has been detected as failed, an entry is in the spares section may be allocated to replace the failed entry. During subsequent accesses to the failed entry, the allocated entry may be used instead. In an embodiment, the failed entry may be coded with an indication of the allocated entry, to redirect to the allocated entry. In one implementation, for example, the failed entry may be coded with N copies of a pointer to the allocated entry, each copy protected by corresponding ECC.
    Type: Application
    Filed: September 22, 2016
    Publication date: March 30, 2017
    Inventors: Manu Gulati, Sukalpa Biswas, Jeffrey R. Wilcox, Farid Nemati
  • Patent number: 9520447
    Abstract: Arrays of memory cells having a common gate terminal and methods of operating and forming the same are described herein. As an example, an array of memory cells may include a group of memory cells each having a resistive storage element coupled to a select device. Each select device includes a first terminal, a second terminal, and a gate terminal, where the gate terminal is common to each memory cell of the group.
    Type: Grant
    Filed: June 16, 2015
    Date of Patent: December 13, 2016
    Assignee: Micron Technology, Inc.
    Inventors: Rajesh N. Gupta, Farid Nemati
  • Patent number: 9472279
    Abstract: A memory system and dynamic memory cell programming process thereof is disclosed. The dynamic programming processes comprises the processes of: (a) determining a concurrent-programmable bit number in accordance with a current budget limit; (b) identifying, with a memory controller, a memory cell in a plurality of memory cells in need of programming; (c) performing programming operation on at least one of the memory cells in need of programming; (d) detecting, with a write-detection unit, an programming operation status of the memory cell being programmed and correspondingly generating a program completion indication; and (e) triggering programming operation to a subsequent one of the memory cells according to the program completion indication from the write-detection unit.
    Type: Grant
    Filed: January 20, 2015
    Date of Patent: October 18, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Yi-Chun Shih, Farid Nemati
  • Publication number: 20160211018
    Abstract: A memory system and dynamic memory cell programming process thereof is disclosed. The dynamic programming processes comprises the processes of: (a) determining a concurrent-programmable bit number in accordance with a current budget limit; (b) identifying, with a memory controller, a memory cell in a plurality of memory cells in need of programming; (c) performing programming operation on at least one of the memory cells in need of programming; (d) detecting, with a write-detection unit, an programming operation status of the memory cell being programmed and correspondingly generating a program completion indication; and (e) triggering programming operation to a subsequent one of the memory cells according to the program completion indication from the write-detection unit.
    Type: Application
    Filed: January 20, 2015
    Publication date: July 21, 2016
    Inventors: YI-CHUN SHIH, FARID NEMATI
  • Patent number: 9361966
    Abstract: Some embodiments include thyristors having first and second electrode regions, first and second base regions, and material having a bandgap of at least 1.2 eV in at least one of the regions. The first base region is between the first electrode region and the second base region, and the second base region is between the second electrode region and the first base region. The first base region interfaces with the first electrode region at a first junction, and interfaces with the second base region at a second junction. The second base region interfaces with the second electrode region at a third junction. A gate is along the first base region, and in some embodiments does not overlap either of the first and second junctions. Some embodiments include methods of programming thyristors, and some embodiments include methods of forming thyristors.
    Type: Grant
    Filed: August 1, 2013
    Date of Patent: June 7, 2016
    Assignee: Micron Technology, Inc.
    Inventors: Farid Nemati, Scott T. Robins, Rajesh N. Gupta
  • Publication number: 20160078917
    Abstract: Some embodiments include thyristors having first and second electrode regions, first and second base regions, and material having a bandgap of at least 1.2 eV in at least one of the regions. The first base region is between the first electrode region and the second base region, and the second base region is between the second electrode region and the first base region. The first base region interfaces with the first electrode region at a first junction, and interfaces with the second base region at a second junction. The second base region interfaces with the second electrode region at a third junction. A gate is along the first base region, and in some embodiments does not overlap either of the first and second junctions. Some embodiments include methods of programming thyristors, and some embodiments include methods of forming thyristors.
    Type: Application
    Filed: November 20, 2015
    Publication date: March 17, 2016
    Inventors: Farid Nemati, Scott T. Robins, Rajesh N. Gupta
  • Publication number: 20150311254
    Abstract: Arrays of memory cells having a common gate terminal and methods of operating and forming the same are described herein. As an example, an array of memory cells may include a group of memory cells each having a resistive storage element coupled to a select device. Each select device includes a first terminal, a second terminal, and a gate terminal, where the gate terminal is common to each memory cell of the group.
    Type: Application
    Filed: June 16, 2015
    Publication date: October 29, 2015
    Inventors: Rajesh N. Gupta, Farid Nemati
  • Patent number: 9082494
    Abstract: Arrays of memory cells having a common gate terminal and methods of operating and forming the same are described herein. As an example, an array of memory cells may include a group of memory cells each having a resistive storage element coupled to a select device. Each select device includes a first terminal, a second terminal, and a gate terminal, where the gate terminal is common to each memory cell of the group.
    Type: Grant
    Filed: January 13, 2012
    Date of Patent: July 14, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Rajesh N. Gupta, Farid Nemati
  • Publication number: 20150155283
    Abstract: Some embodiments include gated bipolar junction transistors. The transistors may include a base region between a collector region and an emitter region; with a B-C junction being at an interface of the base region and the collector region, and with a B-E junction being at an interface of the base region and the emitter region. The transistors may include material having a bandgap of at least 1.2 eV within one or more of the base, emitter and collector regions. The gated transistors may include a gate along the base region and spaced from the base region by dielectric material, with the gate not overlapping either the B-C junction or the B-E junction. Some embodiments include memory arrays containing gated bipolar junction transistors. Some embodiments include methods of forming gated bipolar junction transistors.
    Type: Application
    Filed: February 4, 2015
    Publication date: June 4, 2015
    Inventors: Rajesh N. Gupta, Farid Nemati, Scott T. Robins
  • Patent number: 8952418
    Abstract: Some embodiments include gated bipolar junction transistors. The transistors may include a base region between a collector region and an emitter region; with a B-C junction being at an interface of the base region and the collector region, and with a B-E junction being at an interface of the base region and the emitter region. The transistors may include material having a bandgap of at least 1.2 eV within one or more of the base, emitter and collector regions. The gated transistors may include a gate along the base region and spaced from the base region by dielectric material, with the gate not overlapping either the B-C junction or the B-E junction. Some embodiments include memory arrays containing gated bipolar junction transistors. Some embodiments include methods of forming gated bipolar junction transistors.
    Type: Grant
    Filed: March 1, 2011
    Date of Patent: February 10, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Rajesh N. Gupta, Farid Nemati, Scott T. Robins
  • Publication number: 20130314986
    Abstract: Some embodiments include thyristors having first and second electrode regions, first and second base regions, and material having a bandgap of at least 1.2 eV in at least one of the regions. The first base region is between the first electrode region and the second base region, and the second base region is between the second electrode region and the first base region. The first base region interfaces with the first electrode region at a first junction, and interfaces with the second base region at a second junction. The second base region interfaces with the second electrode region at a third junction. A gate is along the first base region, and in some embodiments does not overlap either of the first and second junctions. Some embodiments include methods of programming thyristors, and some embodiments include methods of forming thyristors.
    Type: Application
    Filed: August 1, 2013
    Publication date: November 28, 2013
    Applicant: Micron Technology, Inc.
    Inventors: Farid Nemati, Scott T. Robins, Rajesh N. Gupta
  • Patent number: 8576607
    Abstract: An integrated circuit and methods of operating same are described. In an embodiment of the integrated circuit included is an array of memory cells, where each of the memory cells includes a resistance-change storage element and a thyristor-based storage element coupled in series. In embodiments of the methods included are methods for data transfer, data tracking, and operating a memory array.
    Type: Grant
    Filed: June 29, 2011
    Date of Patent: November 5, 2013
    Inventor: Farid Nemati