Abstract: Mechanisms are disclosed for performing efficient lossless encryption and decryption to reduce power consumption and improve the efficiency of processing streams of digital data. An input data stream associated with a stream of input data is received. A discrete wavelet transform is applied to a first serial input data value in the input data stream. Distributed components of the first serial input data value are distributed by computing a cumulative probability that the first serial input data value is less than or equal to a power-of-two range value associated with a power-of-two probability distribution function. An entropy encoded encryption value is computed based on a range variant asymmetrical numeral system based on the power-of-two probability distribution function. The entropy encoded encryption value is unloaded based on one or more computed next states. Compressed serial output data streams are compressed based on the unloaded entropy encoded encryption value.

Abstract: Embodiments of the present invention are video acquisition and processing systems. One embodiment of the present invention, video acquisition and processing systems include a sensor, image signal processor, and video compression and decompression components fully integrated in a single integrated circuit. The integrated sensor and image signal processor feature highly parallel transmission of image data to the video compression and decompression component. This highly parallel, pipelined, special-purpose integrated-circuit implementation offers cost-effective video acquisition and image data processing and an extremely large computational bandwidth with relatively low power consumption and low-latency for processing video signals.

Abstract: Embodiments of the present invention are video acquisition and processing systems. One embodiment of the present invention, video acquisition and processing systems include a sensor, image signal processor, and video compression and decompression components fully integrated in a single integrated circuit. The integrated sensor and image signal processor feature highly parallel transmission of image data to the video compression and decompression component. This highly parallel, pipelined, special-purpose integrated-circuit implementation offers cost-effective video acquisition and image data processing and an extremely large computational bandwidth with relatively low power consumption and low-latency for processing video signals.