Patents by Inventor Fei-Sheng Hsu

Fei-Sheng Hsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210263425
    Abstract: A method includes receiving a device design layout and a scribe line design layout surrounding the device design layout. The device design layout and the scribe line design layout are rotated in different directions. An optical proximity correction (OPC) process is performed on the rotated device design layout and the rotated scribe line design layout. A reticle includes the device design layout and the scribe line design layout is formed after performing the OPC process.
    Type: Application
    Filed: May 7, 2021
    Publication date: August 26, 2021
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsueh-Yi CHUNG, Yung-Cheng CHEN, Fei-Gwo TSAI, Chi-Hung LIAO, Shih-Chi FU, Wei-Ti HSU, Jui-Ping CHUANG, Tzong-Sheng CHANG, Kuei-Shun CHEN, Meng-Wei CHEN
  • Patent number: 8543950
    Abstract: A method and system to automate scan synthesis at register-transfer level (RTL). The method and system will produce scan HDL code modeled at RTL for an integrated circuit modeled at RTL. The method and system comprise computer-implemented steps of performing RTL testability analysis, clock-domain minimization, scan selection, test point selection, scan repair and test point insertion, scan replacement and scan stitching, scan extraction, interactive scan debug, interactive scan repair, and flush/random test bench generation. In addition, the present invention further comprises a method and system for hierarchical scan synthesis by performing scan synthesis module-by-module and then stitching these scanned modules together at top-level. The present invention further comprises integrating and verifying the scan HDL code with other design-for-test (DFT) HDL code, including boundary-scan and logic BIST (built-in self-test).
    Type: Grant
    Filed: June 7, 2012
    Date of Patent: September 24, 2013
    Assignee: Syntest Technologies, Inc.
    Inventors: Laung-Terng (L.-T.) Wang, Augusli Kifli, Fei-Sheng Hsu, Shih-Chia Kao, Xiaoqing Wen, Shyh-Horng Lin, Hsin-Po Wang
  • Publication number: 20120246604
    Abstract: A method and system to automate scan synthesis at register-transfer level (RTL). The method and system will produce scan HDL code modeled at RTL for an integrated circuit modeled at RTL. The method and system comprise computer-implemented steps of performing RTL testability analysis, clock-domain minimization, scan selection, test point selection, scan repair and test point insertion, scan replacement and scan stitching, scan extraction, interactive scan debug, interactive scan repair, and flush/random test bench generation. In addition, the present invention further comprises a method and system for hierarchical scan synthesis by performing scan synthesis module-by-module and then stitching these scanned modules together at top-level. The present invention further comprises integrating and verifying the scan HDL code with other design-for-test (DFT) HDL code, including boundary-scan and logic BIST (built-in self-test).
    Type: Application
    Filed: June 7, 2012
    Publication date: September 27, 2012
    Applicant: Syntest Technologies, Inc.
    Inventors: Laung-Terng (L. -T.) WANG, Augusli Kifli, Fei-Sheng Hsu, Shih-Chia Kao, Xiaoqing Wen, Shyh-Horag Lin, Hsin-Po Wang
  • Patent number: 7970597
    Abstract: A circuit emulator includes emulation resources programmed to emulate a circuit, a clocking system for clocking logic implemented by the emulation resources, a resource interface circuit, a logic analyzer, and a debugger. The resource interface circuit supplies input signals to the emulation resources, stores data representing behavior of signals generated by the emulation resources produces in response to the input signals and configures operating characteristics of the clocking system. Upon detecting a specified event in the selected signals of the emulation resources, the logic analyzer asserts a trigger signal telling the clocking system to stop clocking the emulation resources.
    Type: Grant
    Filed: May 15, 2008
    Date of Patent: June 28, 2011
    Assignee: Springsoft, Inc.
    Inventors: Meng-Chyi Lin, Fei-Sheng Hsu, Sweyyan Shei
  • Patent number: 7904773
    Abstract: A method and apparatus for providing ordered capture clocks to detect or locate faults within N clock domains and faults crossing any two clock domains in a scan-based integrated circuit or circuit assembly in self-test or scan-test mode, where N>1 and each domain has a plurality of scan cells. The method and apparatus will apply an ordered sequence of capture clocks to all scan cells within N clock domains where one or more capture clocks must contain one or more shift clock pulses during the capture operation. A computer-aided design (CAD) method is further developed to realize the method and synthesize the apparatus. In order to further improve the circuit's fault coverage, a CAD method and apparatus are further developed to minimize the memory usage and generate scan patterns for full-scan and feed-forward partial-scan designs containing transparent storage cells, asynchronous set/reset signals, tri-state busses, and low-power gated clocks.
    Type: Grant
    Filed: October 1, 2008
    Date of Patent: March 8, 2011
    Assignee: Syntest Technologies, Inc.
    Inventors: Laung-Terng (L. T.) Wang, Meng-Chyi Lin, Xiaoqing Wen, Hsin-Po Wang, Chi-Chan Hsu, Shih-Chia Kao, Fei-Sheng Hsu
  • Publication number: 20090287468
    Abstract: A circuit emulator includes emulation resources programmed to emulate a circuit, a clocking system for clocking logic implemented by the emulation resources, a resource interface circuit, a logic analyzer, and a debugger. The resource interface circuit supplies input signals to the emulation resources, stores data representing behavior of signals generated by the emulation resources produces in response to the input signals and configures operating characteristics of the clocking system. Upon detecting a specified event in the selected signals of the emulation resources, the logic analyzer asserts a trigger signal telling the clocking system to stop clocking the emulation resources.
    Type: Application
    Filed: May 15, 2008
    Publication date: November 19, 2009
    Applicant: SPRINGSOFT, INC.
    Inventors: Meng-Chyi Lin, Fei-Sheng Hsu, Sweyyan Shei
  • Patent number: 7512851
    Abstract: A method and apparatus time-division demultiplexes and decompresses a compressed input stimulus provided at a selected data rate R1, into a decompressed stimulus, driven at a selected data rate R2, for driving selected scan chains in a scan-based integrated circuit using a plurality of time-division demultiplexors and time-division multiplexors for shifting stimuli and test responses in and out of high-speed I/O pads in order to reduce test time, test cost, and scan pin count. A synthesis method is also proposed for synthesizing the time-division multiplexors, decompressors, compressors, and time-division multiplexors.
    Type: Grant
    Filed: July 29, 2004
    Date of Patent: March 31, 2009
    Assignee: Syntest Technologies, Inc.
    Inventors: Laung-Terng Wang, Khader S. Abdel-Hafez, Xiaoqing Wen, Boryau (Jack) Sheu, Fei-Sheng Hsu, Augusli Kifli, Shyh-Horng Lin, Shianling Wu, Shun-Miin (Sam) Wang, Ming-Tung Chang
  • Publication number: 20090070646
    Abstract: A method and apparatus for providing ordered capture clocks to detect or locate faults within N clock domains and faults crossing any two clock domains in a scan-based integrated circuit or circuit assembly in self-test or scan-test mode, where N>1 and each domain has a plurality of scan cells. The method and apparatus will apply an ordered sequence of capture clocks to all scan cells within N clock domains where one or more capture clocks must contain one or more shift clock pulses during the capture operation. A computer-aided design (CAD) method is further developed to realize the method and synthesize the apparatus. In order to further improve the circuit's fault coverage, a CAD method and apparatus are further developed to minimize the memory usage and generate scan patterns for full-scan and feed-forward partial-scan designs containing transparent storage cells, asynchronous set/reset signals, tri-state busses, and low-power gated clocks.
    Type: Application
    Filed: October 1, 2008
    Publication date: March 12, 2009
    Inventors: Laung-Terng (L.T.) Wang, Meng-Chyi Lin, Xiaoqing Wen, Hsin-Po Wang, Chi-Chan Hsu, Shih-Chia Kao, Fei-Sheng Hsu
  • Patent number: 7331032
    Abstract: A method and system to automate scan synthesis at register-transfer level (RTL). The method and system will produce scan HDL code modeled at RTL for an integrated circuit modeled at RTL. The method and system comprise computer-implemented steps of performing RTL testability analysis, clock-domain minimization, scan selection, test point selection, scan repair and test point insertion, scan replacement and scan stitching, scan extraction, interactive scan debug, interactive scan repair, and flush/random test bench generation. In addition, the present invention further comprises a method and system for hierarchical scan synthesis by performing scan synthesis module-by-module and then stitching these scanned modules together at top-level. The present invention further comprises integrating and verifying the scan HDL code with other design-for-test (DFT) HDL code, including boundary-scan and logic BIST (built-in self-test).
    Type: Grant
    Filed: April 22, 2005
    Date of Patent: February 12, 2008
    Assignee: Syntest Technologies, Inc.
    Inventors: Laung-Terng (L. -T.) Wang, Augusli Kifli, Fei-Sheng Hsu, Xiaoqing Wen, Shih-Chia Kao, Shyh-Horng Lin, Hsin-Po Wang
  • Publication number: 20050235186
    Abstract: A method and apparatus for providing ordered capture clocks to detect or locate faults within N clock domains and faults crossing any two clock domains in a scan-based integrated circuit or circuit assembly in self-test or scan-test mode, where N>1 and each domain has a plurality of scan cells. The method and apparatus will apply an ordered sequence of capture clocks to all scan cells within N clock domains where one or more capture clocks must contain one or more shift clock pulses during the capture operation. A computer-aided design (CAD) method is further developed to realize the method and synthesize the apparatus. In order to further improve the circuit's fault coverage, a CAD method and apparatus are further developed to minimize the memory usage and generate scan patterns for full-scan and feed-forward partial-scan designs containing transparent storage cells, asynchronous set/reset signals, tri-state busses, and low-power gated clocks.
    Type: Application
    Filed: June 14, 2005
    Publication date: October 20, 2005
    Applicant: Syntest Technologies, Inc.
    Inventors: Laung-Terng Wang, Meng-Chyi Lin, Xiaoqing Wen, Hsin-Po Wang, Chi-Chan Hsu, Shih-Chia Kao, Fei-Sheng Hsu
  • Patent number: 6957403
    Abstract: A method and system to automate scan synthesis at register-transfer level (RTL). The method and system will produce scan HDL code modeled at RTL for an integrated circuit modeled at RTL. The method and system comprise computer-implemented steps of performing RTL testability analysis, clock-domain minimization, scan selection, test point selection, scan repair and test point insertion, scan replacement and scan stitching, scan extraction, interactive scan debug, interactive scan repair, and flush/random test bench generation. In addition, the present invention further comprises a method and system for hierarchical scan synthesis by performing scan synthesis module-by-module and then stitching these scanned modules together at top-level. The present invention further comprises integrating and verifying the scan HDL code with other design-for-test (DFT) HDL code, including boundary-scan and logic BIST (built-in self-test).
    Type: Grant
    Filed: March 28, 2002
    Date of Patent: October 18, 2005
    Assignee: Syntest Technologies, Inc.
    Inventors: Laung-Terng Wang, Augusli Kifli, Fei-Sheng Hsu, Shih-Chia Kao, Xiaoqing Wen, Shyh-Horng Lin, Hsin-P Wang
  • Patent number: 6954887
    Abstract: A method and apparatus for providing ordered capture clocks to detect or locate faults within N clock domains and faults crossing any two clock domains in a scan-based integrated circuit or circuit assembly in self-test or scan-test mode, where N>1 and each domain has a plurality of scan cells. The method and apparatus will apply an ordered sequence of capture clocks to all scan cells within N clock domains where one or more capture clocks must contain one or more shift clock pulses during the capture operation. A computer-aided design (CAD) method is further developed to realize the method and synthesize the apparatus. In order to further improve the circuit's fault coverage, a CAD method and apparatus are further developed to minimize the memory usage and generate scan patterns for full-scan and feed-forward partial-scan designs containing transparent storage cells, asynchronous set/reset signals, tri-state busses, and low-power gated clocks.
    Type: Grant
    Filed: March 20, 2002
    Date of Patent: October 11, 2005
    Assignee: Syntest Technologies, Inc.
    Inventors: Laung-Terng (L.-T.) Wang, Meng-Chyi Lin, Xiaoqing Wen, Hsin-Po Wang, Chi-Chan Hsu, Shih-Chia Kao, Fei-Sheng Hsu
  • Publication number: 20050055617
    Abstract: A method and apparatus for time-division demultiplexing and decompressing a compressed input stimulus 421, provided at a selected data-rate R1 421, into a decompressed stimulus 424, 426, 433, 435, driven at a selected data-rate R2 442, for driving selected scan chains in a scan-based integrated circuit 401. The scan-based integrated circuit 401 contains a high-speed clock CK1 443, a low-speed clock CK2 442, and a plurality of scan chains 411, . . . , 418, each scan chain comprising multiple scan cells coupled in series. The method and apparatus comprises using a plurality of time-division demultiplexors (TDDMs) 402, 403 and time-division multiplexors (TDMs) 408, 409 for shifting stimuli 421 and test responses 444 in and out of high-speed I/O pads. When applied to the scan-based integrated circuit 401 embedded with one or more pairs of decompressors 404, 405 and compressors 406, 407, it can further reduce the circuit's test time, test cost, and scan pin count.
    Type: Application
    Filed: July 29, 2004
    Publication date: March 10, 2005
    Inventors: Laung-Terng Wang, Khader Abdel-Hafez, Xiaoqing Wen, Boryau Sheu, Fei-Sheng Hsu, Augusli Kifli, Shyh-Horng Lin, Shianling Wu, Shun-Miin Wang, Ming-Tung Chang
  • Publication number: 20040153926
    Abstract: A method and apparatus to test data and set/reset faults in a scan-based integrated circuit in a selected scan-test mode or self-test mode. The scan-based integrated circuit contains multiple scan chains, each scan chain comprising multiple scan cells coupled in series. The method comprises shifting in a plurality of predetermined stimuli during scan-test or pseudo-random stimuli during self-test to the scan-based integrated circuit, using a set/reset enable (SR_EN) signal 383 and a scan enable (SE) signal 382 to capture faults to each scan cell, and shifting out the test responses for comparison or compaction. The apparatus or set/reset controller 375 further comprises using the set/reset enable (SR_EN) signal 383 and scan enable (SE) signal 382 to selectively propagate data faults or set/reset faults to the scan cells in the integrated circuit.
    Type: Application
    Filed: October 24, 2003
    Publication date: August 5, 2004
    Inventors: Khader S. Abdel-Hafez, Laung-Terng Wang, Augusli Kifli, Fei-Sheng Hsu, Xiaoqing Wen, Meng-Chyi Lin, Hsin-Po Wang
  • Publication number: 20030023941
    Abstract: A method and system to automate scan synthesis at register-transfer level (RTL). The method and system will produce scan HDL code modeled at RTL for an integrated circuit modeled at RTL. The method and system comprise computer-implemented steps of performing RTL testability analysis, clock-domain minimization, scan selection, test point selection, scan repair and test point insertion, scan replacement and scan stitching, scan extraction, interactive scan debug, interactive scan repair, and flush/random test bench generation. In addition, the present invention further comprises a method and system for hierarchical scan synthesis by performing scan synthesis module-by-module and then stitching these scanned modules together at top-level. The present invention further comprises integrating and verifying the scan HDL code with other design-for-test (DFT) HDL code, including boundary-scan and logic BIST (built-in self-test).
    Type: Application
    Filed: March 28, 2002
    Publication date: January 30, 2003
    Inventors: Laung-Terng (L.-T.) Wang, Augusli Kifli, Fei-Sheng Hsu, Shih-Chia Kao, Xiaoqing Wen, Shyh-Horng Lin, Hsin-Po Wang
  • Publication number: 20020184560
    Abstract: A method and apparatus for providing ordered capture clocks to detect or locate faults within N clock domains and faults crossing any two clock domains in a scan-based integrated circuit or circuit assembly in self-test or scan-test mode, where N>1 and each domain has a plurality of scan cells. The method and apparatus will apply an ordered sequence of capture clocks to all scan cells within N clock domains where one or more capture clocks must contain one or more shift clock pulses during the capture operation. A computer-aided design (CAD) method is further developed to realize the method and synthesize the apparatus. In order to further improve the circuit's fault coverage, a CAD method and apparatus are further developed to minimize the memory usage and generate scan patterns for full-scan and feed-forward partial-scan designs containing transparent storage cells, asynchronous set/reset signals, tri-state busses, and low-power gated clocks.
    Type: Application
    Filed: March 20, 2002
    Publication date: December 5, 2002
    Inventors: Laung-Terng Wang, Meng-Chyi Lin, Xiaoqing Wen, Hsin-Po Wang, Chi-Chan Hsu, Shih-Chia Kao, Fei-Sheng Hsu