Abstract: Embodiments herein describe integrity check techniques that are efficient and flexible by using local registers in a segment to store check values which can be used to detect errors in the local configuration data in the same segment. In addition to containing local registers storing the check values, each segment can include a mask register indicated which of the configuration registers should be checked and which can be ignored. Further, the segments can include a next segment register indicating the next segment the check engine should evaluate for errors.

Abstract: Techniques to update firmware without a system reset include preserving state information associated with one or more firmware services, suspending processing of firmware service requests, loading an updated firmware image, and resuming processing of firmware service requests based on the preserved state information and the updated firmware image. Unpreserved states of one or more other firmware services may be recreated upon resumption of processing of the firmware service requests.

Abstract: Apparatus and associated methods relate to authenticating a back-to-front-built configuration image. In an illustrative example, a circuit may include memory configured to store a signature S, a second hash H2, and a first data chunk C1. Signature S may be signed on a first hash H1. H1 may be the hash for H2 and C1. If signature S passes verification, a hash engine may perform hash functions on C1 and H2 to generate a hash H1?. H1? may be compared with H1 to indicate whether C1 has been tampered with or not. By using the incremental authentication, a signature that appears at the beginning of the image may be extended to the entire image while only using a small internal buffer. Advantageously, internal buffer may only need to store two hashes Hi, Hi+1, and a data chunk Ci, or, a signature S, a hash Hi, and a data chunk Ci.

Abstract: An input-output circuit is coupled to a plurality of serial communication paths and to a physical point-to-point interface. The input-output circuit is configured to transmit data received on the plurality of serial communication paths over the physical point-to-point interface. An application circuit is coupled to the input-output circuit and is configured to communicate via a first one of the paths in performing application functions. A bridge circuit is coupled to the input-output circuit and is configured to communicate via a second one of the paths. A debug circuit is coupled to the application circuit and to the bridge circuit. The debug circuit is configured to capture debug data of the application circuit and provide the debug data to the bridge circuit for communication via the second one of the paths.

Abstract: A circuit arrangement includes one or more input buffers disposed on a system-on-chip (SoC) and configured to receive and store streaming debug packets. One or more response buffers are also disposed on the SoC. A transaction control circuit is disposed on the SoC and is configured to process each debug packet in the one or more input buffers. The processing includes decoding an operation code in the debug packet, and determining from an address in the debug packet, an interface circuit of multiple interface circuits to access a storage circuit in a subsystem of multiple sub-systems on the SoC. The processing further includes issuing a request via the interface circuit to access the storage circuit according to the operation code, and storing responses and data received from the interface circuits in the one or more response buffers.

Abstract: A circuit arrangement includes one or more input buffers disposed on a system-on-chip (SoC) and configured to receive and store streaming debug packets. One or more response buffers are also disposed on the SoC. A transaction control circuit is disposed on the SoC and is configured to process each debug packet in the one or more input buffers. The processing includes decoding an operation code in the debug packet, and determining from an address in the debug packet, an interface circuit of multiple interface circuits to access a storage circuit in a subsystem of multiple sub-systems on the SoC. The processing further includes issuing a request via the interface circuit to access the storage circuit according to the operation code, and storing responses and data received from the interface circuits in the one or more response buffers.

Abstract: The exemplary embodiments described herein relate to systems and methods for operating system aware low latency handling. One embodiment relates to a non-transitory computer readable storage medium including a set of instructions executable by a processor, the set of instructions, when executed, resulting in a performance of receiving a fast interrupt request asserted by a hardware device while the processor is executing within a kernel critical section, executing a fast interrupt handler at a first priority level, raising a second priority level interrupt by the fast interrupt handler based on the fast interrupt request, wherein the second priority level interrupt invokes a kernel service and processing the second priority level interrupt once the processor has executed the kernel critical section.

Abstract: Apparatus and methods for handling inter-processor interrupts (IPIs) in a heterogeneous multiprocessor system are provided. The scalable IPI mechanism provided herein entails minimal logic and can be used for heterogeneous inter-processor communication, such as between application processors, real-time processors, and FPGA accelerators. This mechanism is also low cost, in terms of both logic area and programmable complexity. One example system generally includes a first processor, a second processor being of a different processor type than the first processor, and an IPI circuit. The IPI circuit typically includes a first register associated with the first processor, wherein a first bit in the first register indicates whether the first processor has requested to interrupt the second processor; and a second register associated with the second processor, wherein a second bit in the second register indicates whether the second processor has requested to interrupt the first processor.

Abstract: A method for extracting static information from user code, analyzing the static information to determine location expressions for program information and comparing the location expressions to reference location expressions of the user code. In addition, a system having a reading module configured to read and extract static information from user code, an analyzing module configured to analyze the static information to determine location expressions for program information and a comparison module configured to compare the location expressions to reference location expressions of the user code.

Abstract: Apparatus and methods for handling inter-processor interrupts (IPIs) in a heterogeneous multiprocessor system are provided. The scalable IPI mechanism provided herein entails minimal logic and can be used for heterogeneous inter-processor communication, such as between application processors, real-time processors, and FPGA accelerators. This mechanism is also low cost, in terms of both logic area and programmable complexity. One example system generally includes a first processor, a second processor being of a different processor type than the first processor, and an IPI circuit. The IPI circuit typically includes a first register associated with the first processor, wherein a first bit in the first register indicates whether the first processor has requested to interrupt the second processor; and a second register associated with the second processor, wherein a second bit in the second register indicates whether the second processor has requested to interrupt the first processor.

Abstract: The exemplary embodiments described herein relate to systems and methods for operating system aware low latency handling. One embodiment relates to a non-transitory computer readable storage medium including a set of instructions executable by a processor, the set of instructions, when executed, resulting in a performance of receiving a fast interrupt request asserted by a hardware device while the processor is executing within a kernel critical section, executing a fast interrupt handler at a first priority level, raising a second priority level interrupt by the fast interrupt handler based on the fast interrupt request, wherein the second priority level interrupt invokes a kernel service and processing the second priority level interrupt once the processor has executed the kernel critical section.

Abstract: A system and method for executing application code in an operating system environment, attaching a development tool to the application code, saving a state of the application code, determining whether the attachment of the development tool interrupted a blocking system call of the application code, modifying, when it is determined the attachment of the development tool interrupted the blocking system call, the saved state to a further saved state corresponding to restarting the blocking system call and restoring the state of the application code to the further saved state.

Abstract: A method including creating a storage buffer in a portion of memory of a computing device; inserting an instrumentation point in software of a further computing device, the instrumentation point corresponding to an event monitored by a hardware trace device, data corresponding to the event being stored in the storage buffer; executing the software; and processing the data, wherein the data is processed after a completion of the execution of the code.

Abstract: A system comprising a memory storing a set of instructions executable by a processor. The instructions being operable to monitor progress of an application executing in a first operating system (OS) instance, the progress occurring on data stored within a shared memory area, detect a failover event in the application and copy, upon the detection of the failover event, the data from the shared memory area to a fail memory area of a second instance of the OS, the fail memory area being an area of memory mapped for receiving data from another instance of the OS only if the application executing on the another instance experiences a failover event.

Abstract: Described herein are systems and tools for scalable handling of debug information. The system includes a memory storing an application, and a processor executing a set of instructions operable to generate a plurality of subsets from the application, produce a linkable file for each of the subsets, each linkable file including debug information for the corresponding subset, create a path from the application to the linkable files based on linked information, and load one of the linkable files for a selected subset.

Abstract: A system and method for inserting at least one instrumentation point into a program at a first location, executing the program and removing the instrumentation point from the program when the executing program reaches the instrumentation point. The system and method further recording the at least one instrumentation point in a record when the instrumentation point is removed from the program.

Abstract: A method for extracting static information from user code, analyzing the static information to determine location expressions for program information and comparing the location expressions to reference location expressions of the user code. In addition, a system having a reading module configured to read and extract static information from user code, an analyzing module configured to analyze the static information to determine location expressions for program information and a comparison module configured to compare the location expressions to reference location expressions of the user code.

Abstract: A system and method for executing application code in an operating system environment, attaching a development tool to the application code, saving a state of the application code, determining whether the attachment of the development tool interrupted a blocking system call of the application code, modifying, when it is determined the attachment of the development tool interrupted the blocking system call, the saved state to a further saved state corresponding to restarting the blocking system call and restoring the state of the application code to the further saved state.

Abstract: A system and method for inserting a marker in an object file, the marker indicating that at least a portion of the object file is subject to a first license agreement, determining if the first license agreement of the object file and a second license agreement to which one of the object file and a further object file to which the object file is linked are incompatible and when the first license agreement and the second license agreement are incompatible, displaying an error message to a user.

Abstract: Described is receiving a segment of source code, analyzing the source code based on a performance metric, wherein the performance metric relates the source code to corresponding machine code and displaying a marked version of the source code, wherein the marked version corresponds to a value of the performance metric.