Patents by Inventor Feng-Ming Chang

Feng-Ming Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210057422
    Abstract: Systems and methods are provided for forming an intra-connection structure. A first gate structure and a first source/drain region adjacent to the first gate structure is formed on a substrate. A first dielectric material is disposed on the first source/drain region. A spacer material is formed on the first gate structure. The first dielectric material is removed to expose at least part of the first source/drain region. At least part of the spacer material is removed to expose at least part of the first gate structure. A first conductive material is formed between the first gate structure and the first source/drain region to electrically connect the first source/drain region and the first gate structure.
    Type: Application
    Filed: November 9, 2020
    Publication date: February 25, 2021
    Inventors: Feng-Ming Chang, Kuo-Hsiu Hsu
  • Patent number: 10880982
    Abstract: A light generation system is provided. The light generation system includes a vaporization device, a laser device and a lens structure. The vaporization device is configured to vaporize a metal-nonmetal compound to generate a metal-nonmetal precursor gas. The laser device is configured to provide laser light, and irradiate the metal-nonmetal precursor gas released from the vaporization device with the laser light to emit a light signal. The lens structure is configured to direct the light signal toward a photomask used in a lithography process.
    Type: Grant
    Filed: June 12, 2019
    Date of Patent: December 29, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Ching-Hsiang Hsu, Feng Yuan Hsu, Hsu-Kai Chang, Chi-Ming Yang
  • Patent number: 10868019
    Abstract: A semiconductor device includes: a first well having a first conductivity-type extending along a first direction; second and third wells having a second conductivity-type and disposed on opposite sides of the first well in a second direction; a first array of bitcells and a second array of bitcells disposed on the first to third wells; a strap cell disposed on the first to third wells and between the first and second arrays and including first and second well pickup regions having the first conductivity-type, disposed on the first well, and spaced-apart from each other in the first direction, and third and fourth well pickup regions having the second conductivity-type and disposed on the second and third wells, respectively; first and second conductive patterns electrically connected to the first and second well pickup regions, respectively; and a third conductive pattern electrically connected to the third and fourth well pickup regions.
    Type: Grant
    Filed: May 5, 2020
    Date of Patent: December 15, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuo-Hung Lo, Feng-Ming Chang, Ying-Hsiu Kuo, Ping-Wei Wang
  • Patent number: 10854279
    Abstract: A SRAM array is provided, including a first bit cell array and a second bit cell array arranged along a first direction; a strap cell arranged in a second direction and positioned between the first bit cell array and the second bit cell array along the first direction. The strap cell includes a first strap column, a second strap column, a doped P-type region, a doped N-type region, and a deep N-type well region. The first strap column includes a first P-type well region and two first N-type well regions adjacent opposite sides of the first P-type well region along the first direction. The second strap column is adjacent to the first strap column along the second direction. The second strap column includes a second N-type well region and two second P-type well regions adjacent opposite sides of the second N-type well region along the first direction.
    Type: Grant
    Filed: July 6, 2020
    Date of Patent: December 1, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chia-Hao Pao, Kian-Long Lim, Feng-Ming Chang, Lien-Jung Hung
  • Patent number: 10840251
    Abstract: A static random access memory device includes a write circuit, a read port circuit, and a substrate. The write port circuit includes a first inverter, a second inverter cross-coupled with the first inverter, a first pass-gate transistor coupled to the first inverter, and a second pass-gate transistor coupled to the second inverter. The read port circuit includes a read pull-down transistor and a read pass-gate transistor that are coupled in series to each other. The substrate includes a standard threshold voltage (STV) region and a low threshold voltage (LVT) region abutting the STV region. The write port circuit is formed within the STV region, and the read port circuit is formed within the LVT region. The LVT region has a first boundary at an edge of a gate of the first pass-gate transistor, or approaching the edge of the gate of the first pass-gate transistor.
    Type: Grant
    Filed: May 20, 2019
    Date of Patent: November 17, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuo-Hung Lo, Feng-Ming Chang, Ying-Hsiu Kuo
  • Patent number: 10833090
    Abstract: Systems and methods are provided for forming an intra-connection structure. A first gate structure and a first source/drain region adjacent to the first gate structure is formed on a substrate. A first dielectric material is disposed on the first source/drain region. A spacer material is formed on the first gate structure. The first dielectric material is removed to expose at least part of the first source/drain region. At least part of the spacer material is removed to expose at least part of the first gate structure. A first conductive material is formed between the first gate structure and the first source/drain region to electrically connect the first source/drain region and the first gate structure.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: November 10, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Feng-Ming Chang, Kuo-Hsiu Hsu
  • Publication number: 20200343185
    Abstract: An SRAM device and method of forming include pass gate (PG), pull-down (PD), and pull-up (PU) transistors. A first gate line of the PG and a second gate line of the PD and the PU extend in a first direction. A common source/drain of the PG, PD, and PU transistors interposes the first and second gate lines and another source/drain of the PG transistor. A first contact extends from the common source/drain and a second contact extends from the another source/drain. A third contact is disposed above the second contact with a first width in the first direction and a first length in a second direction, first length being greater than the first width.
    Type: Application
    Filed: April 25, 2019
    Publication date: October 29, 2020
    Inventors: Chao-Yuan CHANG, Jui-Lin CHEN, Kian-Long LIM, Feng-Ming CHANG
  • Publication number: 20200335155
    Abstract: A SRAM array is provided, including a first bit cell array and a second bit cell array arranged along a first direction; a strap cell arranged in a second direction and positioned between the first bit cell array and the second bit cell array along the first direction. The strap cell includes a first strap column, a second strap column, a doped P-type region, a doped N-type region, and a deep N-type well region. The first strap column includes a first P-type well region and two first N-type well regions adjacent opposite sides of the first P-type well region along the first direction. The second strap column is adjacent to the first strap column along the second direction. The second strap column includes a second N-type well region and two second P-type well regions adjacent opposite sides of the second N-type well region along the first direction.
    Type: Application
    Filed: July 6, 2020
    Publication date: October 22, 2020
    Inventors: Chia-Hao PAO, Kian-Long LIM, Feng-Ming CHANG, Lien-Jung HUNG
  • Publication number: 20200335508
    Abstract: An SRAM structure is provided. The SRAM structure includes a plurality of first well regions with a first doping type, a second well region with a second doping type, a plurality of first well pick-up regions, a plurality of second well pick-up regions and a plurality of memory cells. The first well regions are formed in a semiconductor substrate. The second well region is formed in the semiconductor substrate. The first well pick-up regions are formed in the first well regions. The second well pick-up regions are formed in the second well region. Each of the memory cells is disposed on two adjacent first well regions and a portion of the second well region between the two adjacent first well regions. Each of the first well pick-up regions is disposed between two adjacent second well pick-up regions.
    Type: Application
    Filed: July 6, 2020
    Publication date: October 22, 2020
    Inventors: Feng-Ming CHANG, Chia-Hao PAO, Lien-Jung HUNG, Ping-Wei WANG
  • Publication number: 20200328502
    Abstract: An antenna includes a carrier and at least one conductive component. The carrier may be formed using a composite plastic material. The carrier may provide at least one containing area. The composite plastic material may have a dielectric constant. The at least one conductive component may be formed at the at least one containing area to be combined with the carrier. The at least one conductive component may form a pattern. The dielectric constant may be between a first value and a second value where the first value and the second value are larger than zero, and the first value is smaller than the second value. The first value is substantially six.
    Type: Application
    Filed: October 15, 2019
    Publication date: October 15, 2020
    Inventors: Shu-Te Tai, Chee Ming Eea, Yu-Hsun Huang, Feng-Pin Chang
  • Publication number: 20200302895
    Abstract: A display device and an operating method thereof are provided. The display device includes a display panel, a connector, a controller and a multiplexer. The display panel is configured to simultaneously display a plurality of images of a plurality of external hosts. The connector is configured to connect at least one peripheral apparatus. The controller is coupled to the display panel, the connector and the external hosts, and configured to generate a control signal. The multiplexer is coupled between the controller, the connector and the external hosts, and configured to switch an access right of the at least one peripheral apparatus to one of the external hosts according to the control signal. The controller receives switching information from the external hosts and generates the control signal according to the switching information.
    Type: Application
    Filed: May 29, 2019
    Publication date: September 24, 2020
    Applicant: Wistron Corporation
    Inventors: Feng-Yuan Chen, Chou-Chieh Chang, Kang-Ming Peng, Cheng-I Shih
  • Publication number: 20200272781
    Abstract: A method includes laying out a standard cell region, with a rectangular space being within the standard cell region. The standard cell region includes a first row of standard cells having a first bottom boundary facing the rectangular space, and a plurality of standard cells having side boundaries facing the rectangular space. The plurality of standard cells include a bottom row of standard cells. A memory array is laid out in the rectangular space, and a second bottom boundary of the bottom row and a third bottom boundary of the memory array are aligned to a same straight line. A filler cell region is laid out in the rectangular space. The filler cell region includes a first top boundary contacting the first bottom boundary of the first row of standard cells, and a fourth bottom boundary contacting a second top boundary of the memory array.
    Type: Application
    Filed: December 20, 2019
    Publication date: August 27, 2020
    Inventors: Feng-Ming Chang, Ruey-Wen Chang, Ping-Wei Wang, Sheng-Hsiung Wang, Chi-Yu Lu
  • Publication number: 20200266200
    Abstract: A semiconductor device includes: a first well having a first conductivity-type extending along a first direction; second and third wells having a second conductivity-type and disposed on opposite sides of the first well in a second direction; a first array of bitcells and a second array of bitcells disposed on the first to third wells; a strap cell disposed on the first to third wells and between the first and second arrays and including first and second well pickup regions having the first conductivity-type, disposed on the first well, and spaced-apart from each other in the first direction, and third and fourth well pickup regions having the second conductivity-type and disposed on the second and third wells, respectively; first and second conductive patterns electrically connected to the first and second well pickup regions, respectively; and a third conductive pattern electrically connected to the third and fourth well pickup regions.
    Type: Application
    Filed: May 5, 2020
    Publication date: August 20, 2020
    Inventors: Kuo-Hung LO, Feng-Ming CHANG, Ying-Hsiu KUO, Ping-Wei WANG
  • Publication number: 20200251476
    Abstract: Fin-based well straps are disclosed for improving performance of memory arrays, such as static random access memory arrays. An exemplary well strap cell is disposed between a first memory cell and a second memory cell. The well strap cell includes a p-well, a first n-well, and a second n-well disposed in a substrate. The p-well, the first n-well, and the second n-well are configured in the well strap cell such that a middle portion of the well strap cell is free of the first n-well and the second n-well along a gate length direction. The well strap cell further includes p-well pick up regions to the p-well and n-well pick up regions to the first n-well, the second n-well, or both. The p-well has an I-shaped top view along the gate length direction.
    Type: Application
    Filed: August 1, 2019
    Publication date: August 6, 2020
    Inventors: Feng-Ming Chang, Chia-Hao Pao, Lien Jung Hung, Ping-Wei Wang
  • Patent number: 10723841
    Abstract: A method for preparing a compound and a method for preparing a polymer employing the same are provided. The method for preparing a compound includes reacting a compound having a structure represented by Formula (I) with a compound having a structure represented by Formula (III) in the presence of a compound having a structure represented by Formula (II) to obtain a compound having a structure represented by Formula (IV) wherein Ar1 is substituted or unsubstituted aryl group; X is —O—, —S—, or —NH—; R1 is independently hydrogen or C1-6 alkyl group; R2 is hydroxyl group, C1-6 alkyl group, phenyl group, or tolyl group; and R3 is independently C1-6 alkyl group, C5-8 cycloalkyl group, or C2-6 alkoxyalkyl group.
    Type: Grant
    Filed: July 27, 2018
    Date of Patent: July 28, 2020
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH
    Inventors: Po-Hsien Ho, Chih-Hsiang Lin, Feng-Jen Tsai, Cheng-Hsing Fan, Yih-Her Chang, Hsin-Ching Kao, Chien-Ming Chen
  • Patent number: 10714484
    Abstract: An SRAM structure is provided. The SRAM structure includes a plurality of first well regions with a first doping type, a plurality of second well regions with a second doping type, a third well region with the second doping type, a plurality of first well pick-up regions, a plurality of second well pick-up regions, and a plurality of memory cells. The first well regions, the second well regions, and the third well region are formed in a semiconductor substrate. The third well region is adjacent to the second well regions. The first well pick-up regions are formed in the first well regions. The second well pick-up regions are formed in the third well region. The second well pick-up regions are shared by the third well region and the second well regions. The memory cells are formed on the first and second well regions.
    Type: Grant
    Filed: April 16, 2018
    Date of Patent: July 14, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Feng-Ming Chang, Chia-Hao Pao, Lien-Jung Hung, Ping-Wei Wang
  • Patent number: 10714168
    Abstract: A static random access memory (SRAM) array is provided. The SRAM array includes a first bit cell array and a second bit cell array arranged along a first direction. The SRAM array includes a strap cell arranged along a second direction and positioned between the first bit cell array and the second bit cell array along the first direction. The SRAM array includes a deep N-type well region underlying and connected to the first N-type well region and the second N-type well region.
    Type: Grant
    Filed: December 23, 2019
    Date of Patent: July 14, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Chia-Hao Pao, Kian-Long Lim, Feng-Ming Chang, Lien-Jung Hung
  • Patent number: 10672775
    Abstract: A semiconductor device includes: a first well having a first conductivity-type extending along a first direction; second and third wells having a second conductivity-type and disposed on opposite sides of the first well in a second direction; a first array of bitcells and a second array of bitcells disposed on the first to third wells; a strap cell disposed on the first to third wells and between the first and second arrays and including first and second well pickup regions having the first conductivity-type, disposed on the first well, and spaced-apart from each other in the first direction, and third and fourth well pickup regions having the second conductivity-type and disposed on the second and third wells, respectively; first and second conductive patterns electrically connected to the first and second well pickup regions, respectively; and a third conductive pattern electrically connected to the third and fourth well pickup regions.
    Type: Grant
    Filed: December 27, 2018
    Date of Patent: June 2, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuo-Hung Lo, Feng-Ming Chang, Ying-Hsiu Kuo, Ping-Wei Wang
  • Publication number: 20200143874
    Abstract: A static random access memory (SRAM) array is provided. The SRAM array includes a first bit cell array and a second bit cell array arranged along a first direction. The SRAM array includes a strap cell arranged along a second direction and positioned between the first bit cell array and the second bit cell array along the first direction. The SRAM array includes a deep N-type well region underlying and connected to the first N-type well region and the second N-type well region.
    Type: Application
    Filed: December 23, 2019
    Publication date: May 7, 2020
    Inventors: Chia-Hao PAO, Kian-Long LIM, Feng-Ming CHANG, Lien-Jung HUNG
  • Publication number: 20200135744
    Abstract: A semiconductor device includes first, second, third, fourth, and fifth active regions each extending lengthwise along a first direction, wherein the first, second, third, and fourth active regions comprise channel regions and source/drain (S/D) regions of first, second, third, and fourth transistors respectively, and the fifth active region comprises channel regions and S/D regions of fifth and sixth transistors; and first, second, third, fourth, fifth, and sixth gates each extending lengthwise along a second direction perpendicular to the first direction, wherein the first through sixth gates are configured to engage the channel regions of the first through sixth transistors respectively, wherein the first, second, and fifth gates are electrically connected, and wherein one of the S/D regions of the first transistor, one of the S/D regions of the second transistor, the third gate, and the fourth gate are electrically connected.
    Type: Application
    Filed: December 23, 2019
    Publication date: April 30, 2020
    Inventors: Kuo-Hsiu Hsu, Yu-Kuan Lin, Feng-Ming Chang, Lien Jung Hung, Ping-Wei Wang