Abstract: An array substrate and a reflective display substrate are disclosed. The array substrate includes a base, and a plurality of data lines and a plurality of sub-pixels that are disposed on the base. The sub-pixel includes a reflective pixel electrode and a TFT. An orthographic projection of the pixel electrode in each sub-pixel on the base is overlapped with orthographic projections of a first electrode, a first data line and a second data line.

Abstract: An array substrate and a reflective display substrate are disclosed. The array substrate includes a base, and a plurality of data lines and a plurality of sub-pixels that are disposed on the base. The sub-pixel includes a reflective pixel electrode and a TFT. An orthographic projection of the pixel electrode in each sub-pixel on the base is overlapped with orthographic projections of a first electrode, a first data line and a second data line.

Abstract: An array substrate and a reflective display substrate are disclosed. The array substrate includes a base, and a plurality of data lines and a plurality of sub-pixels that are disposed on the base. The sub-pixel includes a reflective pixel electrode and a TFT. An orthographic projection of the pixel electrode in each sub-pixel on the base is overlapped with orthographic projections of a first electrode, a first data line and a second data line.

Abstract: An array substrate and a reflective display substrate are disclosed. The array substrate includes a base, and a plurality of data lines and a plurality of sub-pixels that are disposed on the base. The sub-pixel includes a reflective pixel electrode and a TFT. An orthographic projection of the pixel electrode in each sub-pixel on the base is overlapped with orthographic projections of a first electrode, a first data line and a second data line.

Abstract: A display panel includes a driving circuit and a signal line. The signal line includes at least two main signal sub-lines each including a first end and a second end, the first ends of the at least two main signal sub-lines are electrically coupled to each other, and the second ends thereof are electrically coupled to each other. N main signal sub-lines in the at least two main signal sub-lines are directly electrically coupled to the driving circuit. Each of the N main signal sub-lines is a direct-coupled main signal sub-line, and a main signal sub-line in the at least two main signal sub-lines other than the direct-coupled main signal sub-lines is an indirect-coupled main signal sub-line which is not directly electrically coupled to the driving circuit but electrically coupled to the driving circuit via the direct-coupled main signal sub-line, where N is a positive integer.

Abstract: An array substrate and a reflective display substrate are disclosed. The array substrate includes a base, and a plurality of data lines and a plurality of sub-pixels that are disposed on the base. The sub-pixel includes a reflective pixel electrode and a TFT. An orthographic projection of the pixel electrode in each sub-pixel on the base is overlapped with orthographic projections of a first electrode, a first data line and a second data line.

Abstract: The present disclosure is related to a shift register circuit. The shift register circuit may include a shift output circuit and N driving output circuits. N is an integer larger than 1. Among the N driving output circuits, an i-th driving output circuit may be respectively coupled to an i-th driving clock signal terminal of N driving clock signal terminals, a pull-up node of the shift output circuit, and an i-th driving output terminal of N driving output terminals. The i-th driving output circuit may be configured to input an i-th driving clock signal from the i-th driving clock signal terminal to the i-th driving output terminal under a control of the pull-up node, wherein i is a positive integer not greater than N.

Abstract: A shift register unit, a driving method thereof, a gate drive circuit and a display device are provided. The shift register unit includes: an input circuit, an output circuit, a pull-down control circuit and a pull-down circuit; and the output circuit is connected to a first DC power supply terminal, a second clock signal terminal, a pull-up node, a first driving signal output terminal and a second driving signal output terminal respectively, and is configured to output a first power supply signal of the first DC power supply terminal to the first driving signal output terminal under control of the pull-up node.

Abstract: The present disclosure provides a shift register unit, including an input sub-circuitry, a pull-up node control sub-circuitry, a pull-down node control sub-circuitry, a gate driving output sub-circuitry and a carry signal output sub-circuitry. The input sub-circuitry is connected to an input end, a second clock signal input end and a pull-up node. The pull-up node control sub-circuitry is connected to the pull-up node, a pull-down node, a first clock signal input end and a first voltage input end. The pull-down node control sub-circuitry is connected to the pull-down node, the pull-up node, the first clock signal input end, the first voltage input end and a second voltage input end.

Abstract: The present application discloses a touch control array substrate having a plurality of subpixel areas. The touch control army substrate includes a base substrate; an array of a plurality of touch electrode blocks on the base substrate; a plurality of touch signal lines respectively electrically connected to the plurality of touch electrode blocks; and a plurality of auxiliary conductive lines. A first touch electrode block of the plurality of touch electrode blocks is electrically connected to at least a first auxiliary conductive line of the plurality of auxiliary conductive lines at at least two different portions of the first touch electrode block.

Abstract: The present disclosure is related to a shift register circuit. The shift register circuit may include a shift output circuit and N driving output circuits. N is an integer larger than 1. Among the N driving output circuits, an i-th driving output circuit may be respectively coupled to an i-th driving clock signal terminal of N driving clock signal terminals, a pull-up node of the shift output circuit, and an i-th driving output terminal of N driving output terminals. The i-th driving output circuit may be configured to input an i-th driving clock signal from the i-th driving, clock signal terminal to the i-th driving output terminal under a control of the pull-up node, wherein i is a positive integer not greater than N.

Abstract: The present disclosure provides a shift register unit, including an input sub-circuitry, a pull-up node control sub-circuitry, a pull-down node control sub-circuitry, a gate driving output sub-circuitry and a carry signal output sub-circuitry. The input sub-circuitry is connected to an input end, a second clock signal input end and a pull-up node. The pull-up node control sub-circuitry is connected to the pull-up node, a pull-down node, a first clock signal input end and a first voltage input end. The pull-down node control sub-circuitry is connected to the pull-down node, the pull-up node, the first clock signal input end, the first voltage input end and a second voltage input end.

Abstract: A shift register unit, a driving method thereof, a gate drive circuit and a display device are provided. The shift register unit includes: an input circuit, an output circuit, a pull-down control circuit and a pull-down circuit; and the output circuit is connected to a first DC power supply terminal, a second clock signal terminal, a pull-up node, a first driving signal output terminal and a second driving signal output terminal respectively, and is configured to output a first power supply signal of the first DC power supply terminal to the first driving signal output terminal under control of the pull-up node.

Abstract: A pixel driving circuit, a display panel and a driving method thereof, and a display device are provided, the pixel driving circuit including: a driving sub-circuit having a threshold voltage (Vth); a light emission control sub-circuit electrically coupled to the driving sub-circuit; and a data write sub-circuit electrically coupled to the driving sub-circuit and the light emission control sub-circuit, and electrically coupled with the driving sub-circuit at a first node and a second node, and configured to receive a scan signal and a data signal, to set a voltage of the first node to a voltage corresponding to the data signal, and set a voltage of the second node to the threshold voltage under control of the scan signal.

Abstract: A display panel, a manufacturing method thereof, and a display device are provided. The display panel includes a first substrate and a reflective second substrate opposite to each other; a liquid crystal (LC) layer located between the first substrate and the second substrate; a first polarizer layer located at a side of the LC layer far away from the second substrate; a second polarizer layer located between the LC layer and the second substrate, the second polarizer layer being configured to allow transmitted light to have a first polarization direction. In the case where the LC layer is not applied with any voltage, light transmitted through the LC layer and the first polarizer layer has a second polarization direction, and the first polarization is substantially perpendicular to the second polarization direction.

Abstract: The present application discloses a touch control array substrate having a plurality of subpixel areas. The touch control army substrate includes a base substrate; an array of a plurality of touch electrode blocks on the base substrate; a plurality of touch signal lines respectively electrically connected to the plurality of touch electrode blocks; and a plurality of auxiliary conductive lines. A first touch electrode block of the plurality of touch electrode blocks is electrically connected to at least a first auxiliary conductive line of the plurality of auxiliary conductive lines at at least two different portions of the first touch electrode block.

Abstract: A shift register unit, a driving method, a gate drive circuit and a display device are provided. The shift register unit includes: an input sub-circuit used to control an electric potential of the pull-up node, an output sub-circuit used to input a first clock signal from a first clock signal terminal to the output terminal, a pull-down control sub-circuit used to control an electric potential of the pull-down node, a pull-down sub-circuit used to control electric potentials of the pull-up node and the output terminal, a first reset control sub-circuit used to control an electric potential of the second control node under control of the first control node and a reset signal from the reset signal terminal and a reset sub-circuit used to control the electric potential of the pull-up node. The shift register unit improves the noise reduction efficiency at the output terminal.

Abstract: A shift register, a method for driving the same, a gate drive circuit and a display device are provided. The shift register includes a write circuit, a pull-down control circuit and an output circuit. The write circuit is configured to write a write signal provided by a write signal input terminal to a pull-up node. The pull-down control circuit is configured to write a first operating voltage provided by a first power supply terminal to a pull-down node, and write a first clock signal to the pull-down node. The output circuit is configured to write a drive signal provided by a drive signal input terminal to a drive signal output terminal, and write a second operating voltage provided by a second power supply terminal to the drive signal output terminal.

Abstract: A shift register and a driving method thereof, a gate drive circuit and a display device are provided. The shift register may comprise a transmission sub-circuit, a storage sub-circuit and an output control sub-circuit. The shift register may further comprise an output buffer sub-circuit and a reset sub-circuit. The gate drive circuit may comprise a plurality of cascaded shift registers as described above. The display device may comprise the gate drive circuit. The present disclosure guarantees the working stability, use reliability and display effect of a display panel.

Abstract: The disclosure relates to a shift register unit, a driving method of shift register units, a gate driving circuit and a display panel. The shift register unit includes: an input module, a pull-up module, a storage capacitor, an output module configured to transmit a first voltage signal to a signal output terminal under the control of the first voltage signal; and an output control module configured to transmit the first voltage signal or a second power signal to the signal output terminal under the control of the voltage signal of the pull-up node and a first selection signal, and to transmit the first voltage signal or the second power signal to the signal output terminal under the control of the voltage signal of the pull-up node and a second selection signal.