Abstract: This application provides a method, a terminal-side device, and a cloud-side device for data processing and a terminal-cloud collaboration system. The method includes: sending, by the terminal-side device, a request message to the cloud-side device; receiving, by the terminal-side device, a second neural network model that is obtained by compressing a first neural network model and that is sent by the cloud-side device, where the first neural network model is a neural network model on the cloud-side device that is used to process the cognitive computing task, and a hardware resource required when the second neural network model runs on the terminal-side device is within an available hardware resource capability range of the terminal-side device; and processing, by the terminal-side device, the cognitive computing task based on the second neural network model.

Abstract: In a method for selecting pictures from a sequence of pictures of an object in motion, a computerized user device determines, for each picture in the sequence of pictures, a value of a motion feature of the object. Based on analyzing the values of the motion feature of the pictures in the sequence, the device identifies a first subset of pictures from the pictures in the sequence. The device then selects, based on a second selection criterion, a second subset of pictures from the first subset of pictures. The pictures in the second subset are displayed to a user for further selection.

Abstract: An image processing apparatus and a method are provided. The apparatus comprises a plurality of processing modules configured to operate in series to refine a raw image captured by a camera, the modules comprising a first module and a second module, each of which independently implements a respective trained artificial intelligence model, wherein: the first module implements an image transformation operation that performs an operation from the set comprising: (i) an essentially pixel-level operation that increases sharpness of an image input to the module, (ii) an essentially pixel-level operation that decreases sharpness of an image input to the module, (iii) an essentially pixel-block-level operation on an image input to the module; and the second module as a whole implements a different operation from the said set.

Abstract: This application relates to an image enhancement technology in the field of computer vision in the field of artificial intelligence, and provides an image enhancement method and apparatus. This application relates to the field of artificial intelligence, and specifically, to the field of computer vision. The method includes: adjusting a pixel value of a to-be-processed image, to obtain K images, where pixel values of the K images are different, and K is a positive integer greater than 1; extracting local features of the K images; extracting a global feature of the to-be-processed image; and performing image enhancement processing on the to-be-processed image based on the global feature and the local features, to obtain an image-enhanced output image. This method helps to improve the effect of image quality enhancement processing.

Abstract: This application provides an image denoising method and apparatus, and relates to the artificial intelligence field and specifically relates to the computer vision field. The method includes: performing resolution reduction processing on a to-be-processed image to obtain a plurality of images whose resolutions are lower than that of the to-be-processed image; extracting an image feature of a higher-resolution image based on an image feature of a lower-resolution image to obtain an image feature of the to-be-processed image; and performing denoising processing on the to-be-processed image based on the image feature of the to-be-processed image to obtain a denoised image. This application can improve an image denoising effect.

Abstract: In a method for selecting pictures from a sequence of pictures of an object in motion, a computerized user device determines, for each picture in the sequence of pictures, a value of a motion feature of the object. Based on analyzing the values of the motion feature of the pictures in the sequence, the device identifies a first subset of pictures from the pictures in the sequence. The device then selects, based on a second selection criterion, a second subset of pictures from the first subset of pictures. The pictures in the second subset are displayed to a user for further selection.

Abstract: An image processing apparatus and a method are provided. The apparatus comprises a plurality of processing modules configured to operate in series to refine a raw image captured by a camera, the modules comprising a first module and a second module, each of which independently implements a respective trained artificial intelligence model, wherein: the first module implements an image transformation operation that performs an operation from the set comprising: (i) an essentially pixel-level operation that increases sharpness of an image input to the module, (ii) an essentially pixel-level operation that decreases sharpness of an image input to the module, (iii) an essentially pixel-block-level operation on an image input to the module; and the second module as a whole implements a different operation from the said set.

Abstract: A memory access system includes a memory, a controller, and a redundancy elimination unit. The memory is a multi-way set associative memory, and the redundancy elimination unit records M record items. Each record item is used to store a tag of a stored data block in one of storage sets. The controller determines a read data block and a target storage set of the read data block and sends a query message to the redundancy elimination unit. The query message carries a set identifier of the target storage set of the read data block and a tag of the read data block. The redundancy elimination unit determines a record item corresponding to the set identifier of the target storage set, matches the tag of the read data block with a tag of a stored data block in the record item corresponding to the target storage set of the read data block.

Abstract: This application provides a method, a terminal-side device, and a cloud-side device for data processing and a terminal-cloud collaboration system. The method includes: sending, by the terminal-side device, a request message to the cloud-side device; receiving, by the terminal-side device, a second neural network model that is obtained by compressing a first neural network model and that is sent by the cloud-side device, where the first neural network model is a neural network model on the cloud-side device that is used to process the cognitive computing task, and a hardware resource required when the second neural network model runs on the terminal-side device is within an available hardware resource capability range of the terminal-side device; and processing, by the terminal-side device, the cognitive computing task based on the second neural network model.

Abstract: A method for generating an accelerator program is disclosed, to help increase utilization of an accelerator and increase program development efficiency. In some feasible implementations of the present invention, the method includes: obtaining an accelerator program description that is based on a state machine, where the accelerator program description includes multiple state machines separately configured to implement an application program, and the multiple state machines form a pipeline according to a data dependency in a directed acyclic graph DAG corresponding to the application program; and performing state machine splicing on the state machines in the accelerator program description by using an accelerator compilation tool, to generate an accelerator program.

Abstract: Multiple lock assemblies are distributed on a chip, each lock assembly manage a lock application message for applying for a lock and a lock release message for releasing a lock that are sent by one small core. Specifically, embodiments include receiving a lock message sent by a small core, where the lock message carries a memory address corresponding to a lock requested by a first thread in the small core; calculating, using the memory address of the requested lock, a code number of a lock assembly to which the requested lock belongs; and sending the lock message to the lock assembly corresponding to the code number, to request the lock assembly to process the lock message.

Abstract: A method for generating an accelerator program is disclosed, to help increase utilization of an accelerator and increase program development efficiency. In some feasible implementations of the present invention, the method includes: obtaining an accelerator program description that is based on a state machine, where the accelerator program description includes multiple state machines separately configured to implement an application program, and the multiple state machines form a pipeline according to a data dependency in a directed acyclic graph DAG corresponding to the application program; and performing state machine splicing on the state machines in the accelerator program description by using an accelerator compilation tool, to generate an accelerator program.

Abstract: A memory access system includes a memory, a controller, and a redundancy elimination unit. The memory is a multi-way set associative memory, and the redundancy elimination unit records M record items. Each record item is used to store a tag of a stored data block in one of storage sets. The controller determines a read data block and a target storage set of the read data block and sends a query message to the redundancy elimination unit. The query message carries a set identifier of the target storage set of the read data block and a tag of the read data block. The redundancy elimination unit determines a record item corresponding to the set identifier of the target storage set, matches the tag of the read data block with a tag of a stored data block in the record item corresponding to the target storage set of the read data block.

Abstract: A memory access processing method and apparatus, and a system. The method includes receiving a memory access request sent by a processor, combining multiple memory access requests received within a preset time period to form a new memory access request, where the new memory access request includes a code bit vector corresponding to memory addresses. A first code bit identifier is configured for the code bits that are in the code bit vector and corresponding to the memory addresses accessed by the multiple memory access requests. The method further includes sending the new memory access request to a memory controller, so that the memory controller executes a memory access operation on a memory address corresponding to the first code bit identifier. The method effectively improves memory bandwidth utilization.

Abstract: Multiple lock assemblies are distributed on a chip, each lock assembly manage a lock application message for applying for a lock and a lock release message for releasing a lock that are sent by one small core. Specifically, embodiments include receiving a lock message sent by a small core, where the lock message carries a memory address corresponding to a lock requested by a first thread in the small core; calculating, using the memory address of the requested lock, a code number of a lock assembly to which the requested lock belongs; and sending the lock message to the lock assembly corresponding to the code number, to request the lock assembly to process the lock message.

Abstract: Multiple lock assemblies are distributed on a chip, each lock assembly manage a lock application message for applying for a lock and a lock release message for releasing a lock that are sent by one small core. Specifically, embodiments include receiving a lock message sent by a small core, where the lock message carries a memory address corresponding to a lock requested by a first thread in the small core; calculating, using the memory address of the requested lock, a code number of a lock assembly to which the requested lock belongs; and sending the lock message to the lock assembly corresponding to the code number, to request the lock assembly to process the lock message.

Abstract: A memory access processing method and apparatus, and a system. The method includes receiving a memory access request sent by a processor, combining multiple memory access requests received within a preset time period to form a new memory access request, where the new memory access request includes a code bit vector corresponding to memory addresses. A first code bit identifier is configured for the code bits that are in the code bit vector and corresponding to the memory addresses accessed by the multiple memory access requests. The method further includes sending the new memory access request to a memory controller, so that the memory controller executes a memory access operation on a memory address corresponding to the first code bit identifier. The method effectively improves memory bandwidth utilization.

Abstract: Multiple lock assemblies are distributed on a chip, each lock assembly manage a lock application message for applying for a lock and a lock release message for releasing a lock that are sent by one small core. Specifically, embodiments include receiving a lock message sent by a small core, where the lock message carries a memory address corresponding to a lock requested by a first thread in the small core; calculating, using the memory address of the requested lock, a code number of a lock assembly to which the requested lock belongs; and sending the lock message to the lock assembly corresponding to the code number, to request the lock assembly to process the lock message.